Latch inference and how to avoid it in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is latch inference in Verilog?

Latch inference happens when the synthesis tool creates a latch because some outputs are not assigned in all possible conditions inside a combinational always block.

beginner

Why is latch inference usually undesirable in digital design?

Latches can cause timing problems and unpredictable behavior because they hold their previous value without a clock, making circuits harder to debug and slower to operate.

beginner

How can you avoid latch inference in a combinational always block?

Make sure every output signal is assigned a value in every possible path of the always block, including the else parts of if statements or default assignments at the start.

intermediate

What is a common coding pattern to prevent latch inference?

Assign default values to all outputs at the beginning of the always block, then override them conditionally. This ensures outputs always have a value.

intermediate

Show an example of a latch inferred due to missing else branch.

always @(*) begin if (enable) out = in1; // Missing else: out keeps old value, latch inferred end

What causes latch inference in a combinational always block?

A Not assigning outputs in all possible conditions

B Using a clock signal

C Assigning outputs only once

D Using blocking assignments

Latch inference happens when outputs are not assigned in every possible condition, causing the tool to create a latch to hold the previous value.

How can you prevent latch inference?

A Use only non-blocking assignments

B Assign default values to outputs at the start of the always block

C Avoid using if statements

D Use only clocked always blocks

Assigning default values ensures outputs always have a value, preventing latches from being inferred.

Which of these is a sign that a latch might be inferred?

A Using non-blocking assignments

B All outputs are assigned in every branch

C Using always @(posedge clk)

D An output is assigned only inside an if without an else

If an output is assigned only in an if branch and not in else, the tool infers a latch to hold the previous value.

Why are latches generally avoided in synchronous designs?

A They cause timing uncertainty and glitches

B They use too much power

C They are slower than combinational logic

D They require more code

Latches can cause timing uncertainty and glitches because they are level-sensitive and hold values without a clock edge.

What is a good practice when writing combinational always blocks?

A Avoid using else statements

B Use only blocking assignments

C Assign default values to outputs at the start

D Use only asynchronous resets

Assigning default values at the start of the block ensures outputs are always assigned, preventing latch inference.

Explain what latch inference is and why it happens in Verilog.

Think about what happens when outputs are not assigned in all cases.

Describe how to write Verilog code to avoid latch inference.

Consider how to make sure outputs always get a value.