Latch inference and how to avoid it in Verilog - Time & Space Complexity

Time Complexity: Latch inference and how to avoid it

O(n)

Understanding Time Complexity

When writing Verilog, sometimes unintended latches are created. This affects how the hardware behaves and how long it takes to run.

We want to understand how the design's execution steps grow when latches appear or are avoided.

Scenario Under Consideration

Analyze the time complexity of this Verilog code that may cause latch inference.

always @(*) begin
  if (enable) begin
    out = in1;
  end else begin
    out = out; // Explicitly hold value to avoid latch
  end
end
    

This code assigns out only when enable is true, otherwise it keeps previous value, causing a latch.

Identify Repeating Operations

Look for repeated actions that affect timing.

• Primary operation: The conditional check inside the always block runs every time inputs change.
• How many times: This check happens continuously as signals change, but the latch holds state without extra operations.

How Execution Grows With Input

Consider how the hardware reacts as input signals increase.

Input Size (n)	Approx. Operations
10	10 conditional checks, latch holds state
100	100 conditional checks, latch holds state
1000	1000 conditional checks, latch holds state

Pattern observation: The number of checks grows linearly with input changes, but the latch itself does not add extra operations.

Final Time Complexity

Time Complexity: O(n)

This means the number of operations grows linearly with the number of input changes, but the latch holds state without extra repeated work.

Common Mistake

[X] Wrong: "Leaving out an else branch won't affect timing or hardware behavior."

[OK] Correct: Missing else causes latch inference, which changes hardware behavior and can cause unexpected delays or bugs.

Interview Connect

Understanding latch inference shows you know how hardware timing and behavior relate to code. This skill helps you write clear, predictable designs.

Self-Check

"What if we add an else branch that assigns a default value? How would the time complexity change?"

Practice

1. What causes latch inference in Verilog combinational blocks?

easy

A. Assigning default values to outputs

B. Using clocked always blocks

C. Using non-blocking assignments

D. Not assigning output signals in all possible conditions

Solution

1. Step 1: Understand latch inference context

   Latch inference occurs when outputs inside combinational blocks are not assigned in every possible condition.

2. Step 2: Identify cause of latch inference

   If an output is missing assignment in some branches, Verilog infers a latch to hold the previous value.

3. Final Answer:

   Not assigning output signals in all possible conditions -> Option D

4. Quick Check:

   Missing assignments cause latch inference [OK]

Hint: Always assign outputs in every condition to avoid latches [OK]

Common Mistakes:

• Thinking clocked blocks cause latch inference
• Believing non-blocking assignments cause latches
• Ignoring missing else branches

2. Which Verilog code snippet correctly avoids latch inference in a combinational block?

easy

A. always @(*) begin
out = 0;
if (sel) out = 1;
end

B. always @(*) begin
if (sel) out = 1;
end

C. always @(posedge clk) begin
if (sel) out <= 1;
end

D. always @(*) begin
if (sel) out = 1;
else if (sel) out = 0;
end

Solution

1. Step 1: Check for default assignment

   always @(*) begin out = 0; if (sel) out = 1; end assigns a default value to 'out' before conditional checks, preventing latch inference.

2. Step 2: Compare other options

   always @(*) begin if (sel) out = 1; end misses assignment when 'sel' is false, causing latch. always @(posedge clk) begin if (sel) out <= 1; end is clocked, not combinational. always @(*) begin if (sel) out = 1; else if (sel) out = 0; end misses assignment when 'sel' is false since both conditions require sel true, causing latch.

3. Final Answer:

   Assigning default value before conditions to avoid latches -> Option A

4. Quick Check:

   Default assignment prevents latch [OK]

Hint: Assign default output values at start of combinational blocks [OK]

Common Mistakes:

• Omitting default assignments
• Confusing clocked and combinational blocks
• Using incomplete else branches

3. Given the following Verilog code, what is the inferred hardware behavior?

always @(*) begin
  if (a) out = 1;
  else if (b) out = 0;
  // no assignment if neither a nor b
end

medium

A. Latch inferred to hold previous value when neither a nor b is true

B. Combinational logic with no latch

C. Synthesis error due to missing assignments

D. Flip-flop inferred with clock input

Solution

1. Step 1: Analyze assignment coverage

   The code assigns 'out' only when 'a' or 'b' is true; no assignment otherwise.

2. Step 2: Understand latch inference

   Missing assignment in some conditions causes Verilog to infer a latch to hold the last value.

3. Final Answer:

   Latch inferred to hold previous value when neither a nor b is true -> Option A

4. Quick Check:

   Missing else branch causes latch [OK]

Hint: Check if all conditions assign outputs; else latch inferred [OK]

Common Mistakes:

• Assuming no latch because of if-else
• Confusing latch with flip-flop
• Thinking synthesis error occurs

4. Identify the error in this Verilog code that causes latch inference:

always @(*) begin
  if (enable) out = data;
  // no else branch
end

How can it be fixed?

medium

A. Use non-blocking assignments instead of blocking

B. Change always @(*) to always @(posedge clk)

C. Add an else branch assigning a default value to 'out'

D. Remove the if condition entirely

Solution

1. Step 1: Identify missing assignment

   The code assigns 'out' only when 'enable' is true; no assignment otherwise causes latch.

2. Step 2: Fix by adding else branch

   Adding an else branch with a default assignment ensures 'out' is assigned in all cases, avoiding latch.

3. Final Answer:

   Add an else branch assigning a default value to 'out' -> Option C

4. Quick Check:

   Complete assignments prevent latch [OK]

Hint: Always include else branch or default assignment [OK]

Common Mistakes:

• Thinking clocked block fixes latch in combinational logic
• Ignoring missing else branch
• Confusing blocking and non-blocking assignments

5. You want to design a combinational logic block in Verilog that outputs 'result' based on inputs 'x' and 'y'. To avoid latch inference, which of the following coding styles is best?

always @(*) begin
  case ({x,y})
    2'b00: result = 0;
    2'b01: result = 1;
    2'b10: result = 1;
    // missing 2'b11 case
  endcase
end

hard

A. Use an always @(posedge clk) block instead

B. Add a default case assigning 'result' a value

C. Remove the case statement and use if-else only

D. Leave as is; synthesis tools will optimize automatically

Solution

1. Step 1: Identify incomplete case coverage

   The case statement misses the 2'b11 input combination, so 'result' is not assigned in that case.

2. Step 2: Add default case to assign 'result'

   Adding a default case ensures 'result' is assigned for all inputs, preventing latch inference.

3. Final Answer:

   Add a default case assigning 'result' a value -> Option B

4. Quick Check:

   Complete case coverage avoids latch [OK]

Hint: Always cover all cases or use default in case statements [OK]

Common Mistakes:

• Assuming missing case won't cause latch
• Switching to clocked block unnecessarily
• Ignoring default case importance