D flip-flop with asynchronous reset in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with asynchronous reset

Start

↓

Check async reset

|Yes↓

Set Q=0

↓

Wait for clock edge

↓

On rising clock edge

↓

Set Q = D

↓

Loop back to Start

The flip-flop first checks if reset is active asynchronously; if yes, output Q is cleared immediately. Otherwise, on the rising clock edge, Q takes the value of D.

Execution Sample

Verilog

always @(posedge clk or posedge rst) begin
  if (rst)
    Q <= 0;
  else
    Q <= D;
end

This code models a D flip-flop that resets Q to 0 immediately when rst is high, otherwise updates Q to D on the clock's rising edge.

Execution Table

Step	rst	clk	D	Condition	Action	Q (output)
1	0	0	X	rst=0, no clock edge	No change	Q=initial (assume 0)
2	1	0	X	rst=1 (async reset)	Set Q=0 immediately	Q=0
3	0	rising edge	1	rst=0, clk rising	Q <= D	Q=1
4	0	0	0	rst=0, no clock edge	No change	Q=1
5	0	rising edge	0	rst=0, clk rising	Q <= D	Q=0
6	1	0	1	rst=1 (async reset)	Set Q=0 immediately	Q=0
7	0	rising edge	1	rst=0, clk rising	Q <= D	Q=1
8	0	0	X	rst=0, no clock edge	No change	Q=1

💡 Simulation ends after step 8; no further clock edges or resets.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8
rst	0	0	1	0	0	0	1	0	0
clk	0	0	0	rising	0	rising	0	rising	0
D	X	X	X	1	0	0	1	1	X
Q	0	0	0	1	1	0	0	1	1

Key Moments - 3 Insights

Why does Q reset immediately when rst=1 even if clk is not rising?

Because rst is asynchronous, the flip-flop sets Q=0 immediately when rst=1, as shown in execution_table rows 2 and 6.

Why does Q only change to D on the rising edge of clk when rst=0?

The flip-flop updates Q to D only on clk's rising edge if rst=0, as seen in rows 3, 5, and 7 of the execution_table.

What happens if rst goes from 1 to 0 without a clock edge?

Q remains at 0 until the next rising clock edge updates it, shown between rows 6 and 7 where rst=0 but clk has not risen yet.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of Q after the clock rising edge?

A 0

B X (unknown)

C 1

D No change

💡 Hint

Check row 3 in execution_table where clk rises and Q is set to D=1.

At which step does the asynchronous reset set Q to 0 immediately?

A Step 2

B Step 3

C Step 1

D Step 5

💡 Hint

Look at execution_table rows where rst=1 and Q is set to 0 immediately.

If rst stayed at 0 and clk never had a rising edge, what would happen to Q?

A Q would keep changing to D

B Q would stay at its last value

C Q would reset to 0

D Q would become unknown

💡 Hint

Refer to execution_table rows 1 and 4 where no clock edge means no Q change.

Concept Snapshot

D flip-flop with async reset syntax:
always @(posedge clk or posedge rst) begin
  if (rst) Q <= 0; // async reset
  else Q <= D;     // on clock rising edge
end

Async reset clears Q immediately.
Q updates to D only on clk rising edge if rst=0.

Full Transcript

This visual trace shows a D flip-flop with asynchronous reset in Verilog. The flip-flop checks rst first; if rst is high, Q resets to 0 immediately, regardless of the clock. If rst is low, Q updates to the input D only on the rising edge of clk. The execution table walks through steps showing how Q changes with different rst, clk, and D values. The variable tracker records the values of rst, clk, D, and Q at each step. Key moments clarify why Q resets asynchronously and updates only on clock edges. The quiz tests understanding of Q's value changes and reset behavior. This helps beginners see how asynchronous reset and clock-driven data input work together in a D flip-flop.