D flip-flop with asynchronous reset in Verilog - Step-by-Step Execution

Concept Flow - D flip-flop with asynchronous reset

Start

↓

Check async reset

|Yes↓

Set Q=0

↓

Wait for clock edge

↓

On rising clock edge

↓

Set Q = D

↓

Loop back to Start

The flip-flop first checks if reset is active asynchronously; if yes, output Q is cleared immediately. Otherwise, on the rising clock edge, Q takes the value of D.

Execution Sample

Verilog

always @(posedge clk or posedge rst) begin
  if (rst)
    Q <= 0;
  else
    Q <= D;
end

This code models a D flip-flop that resets Q to 0 immediately when rst is high, otherwise updates Q to D on the clock's rising edge.

Execution Table

Step	rst	clk	D	Condition	Action	Q (output)
1	0	0	X	rst=0, no clock edge	No change	Q=initial (assume 0)
2	1	0	X	rst=1 (async reset)	Set Q=0 immediately	Q=0
3	0	rising edge	1	rst=0, clk rising	Q <= D	Q=1
4	0	0	0	rst=0, no clock edge	No change	Q=1
5	0	rising edge	0	rst=0, clk rising	Q <= D	Q=0
6	1	0	1	rst=1 (async reset)	Set Q=0 immediately	Q=0
7	0	rising edge	1	rst=0, clk rising	Q <= D	Q=1
8	0	0	X	rst=0, no clock edge	No change	Q=1

💡 Simulation ends after step 8; no further clock edges or resets.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8
rst	0	0	1	0	0	0	1	0	0
clk	0	0	0	rising	0	rising	0	rising	0
D	X	X	X	1	0	0	1	1	X
Q	0	0	0	1	1	0	0	1	1

Key Moments - 3 Insights

Why does Q reset immediately when rst=1 even if clk is not rising?

Because rst is asynchronous, the flip-flop sets Q=0 immediately when rst=1, as shown in execution_table rows 2 and 6.

Why does Q only change to D on the rising edge of clk when rst=0?

The flip-flop updates Q to D only on clk's rising edge if rst=0, as seen in rows 3, 5, and 7 of the execution_table.

What happens if rst goes from 1 to 0 without a clock edge?

Q remains at 0 until the next rising clock edge updates it, shown between rows 6 and 7 where rst=0 but clk has not risen yet.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of Q after the clock rising edge?

A 0

B X (unknown)

C 1

D No change

💡 Hint

Check row 3 in execution_table where clk rises and Q is set to D=1.

At which step does the asynchronous reset set Q to 0 immediately?

A Step 2

B Step 3

C Step 1

D Step 5

💡 Hint

Look at execution_table rows where rst=1 and Q is set to 0 immediately.

If rst stayed at 0 and clk never had a rising edge, what would happen to Q?

A Q would keep changing to D

B Q would stay at its last value

C Q would reset to 0

D Q would become unknown

💡 Hint

Refer to execution_table rows 1 and 4 where no clock edge means no Q change.

Concept Snapshot

D flip-flop with async reset syntax:
always @(posedge clk or posedge rst) begin
  if (rst) Q <= 0; // async reset
  else Q <= D;     // on clock rising edge
end

Async reset clears Q immediately.
Q updates to D only on clk rising edge if rst=0.

Full Transcript

This visual trace shows a D flip-flop with asynchronous reset in Verilog. The flip-flop checks rst first; if rst is high, Q resets to 0 immediately, regardless of the clock. If rst is low, Q updates to the input D only on the rising edge of clk. The execution table walks through steps showing how Q changes with different rst, clk, and D values. The variable tracker records the values of rst, clk, D, and Q at each step. Key moments clarify why Q resets asynchronously and updates only on clock edges. The quiz tests understanding of Q's value changes and reset behavior. This helps beginners see how asynchronous reset and clock-driven data input work together in a D flip-flop.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic