D flip-flop with asynchronous reset in Verilog - Mini Project: Build & Apply

D flip-flop with asynchronous reset

📖 Scenario: You are designing a simple digital circuit component called a D flip-flop. This flip-flop stores a single bit of data and can be reset asynchronously.

🎯 Goal: Build a Verilog module for a D flip-flop with an asynchronous reset input.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d, clk, and reset, and output q.

Implement asynchronous reset that sets q to 0 immediately when reset is high.

On the rising edge of clk, if reset is low, q should take the value of d.

💡 Why This Matters

🌍 Real World

D flip-flops are basic building blocks in digital circuits used for storing bits and synchronizing data.

💼 Career

Understanding flip-flops is essential for hardware design engineers working with FPGAs, ASICs, and digital systems.

1

Create the module and declare inputs and outputs

Write a Verilog module named d_flip_flop with inputs d, clk, and reset, and output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

// Your code here

endmodule

Need a hint?

Start by writing the module header with the correct inputs and outputs.

2

Add asynchronous reset logic

Inside the module, add an always block that is sensitive to posedge clk and posedge reset. This block will handle the asynchronous reset.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Need a hint?

Use always @(posedge clk or posedge reset) to detect clock and reset changes.

3

Implement reset and data capture behavior

Inside the always block, write an if statement that sets q to 0 when reset is high. Otherwise, set q to d on the rising edge of clk.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Your code here
    end else begin
        // Your code here
    end
end

endmodule

Need a hint?

Use non-blocking assignments <= to update q.

4

Test the D flip-flop output

Add a initial block to simulate the flip-flop behavior. Initialize reset to 1, then 0, and toggle clk while changing d. Use $display to print q after each clock edge.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

initial begin
    // Your code here
end

Need a hint?

Use initial block and $display to simulate and print values.