D flip-flop with asynchronous reset in Verilog - Mini Project: Build & Apply

D flip-flop with asynchronous reset

📖 Scenario: You are designing a simple digital circuit component called a D flip-flop. This flip-flop stores a single bit of data and can be reset asynchronously.

🎯 Goal: Build a Verilog module for a D flip-flop with an asynchronous reset input.

📋 What You'll Learn

Create a module named d_flip_flop with inputs d, clk, and reset, and output q.

Implement asynchronous reset that sets q to 0 immediately when reset is high.

On the rising edge of clk, if reset is low, q should take the value of d.

💡 Why This Matters

🌍 Real World

D flip-flops are basic building blocks in digital circuits used for storing bits and synchronizing data.

💼 Career

Understanding flip-flops is essential for hardware design engineers working with FPGAs, ASICs, and digital systems.

1

Create the module and declare inputs and outputs

Write a Verilog module named d_flip_flop with inputs d, clk, and reset, and output q. Declare q as a reg type.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

// Your code here

endmodule

Hint

Start by writing the module header with the correct inputs and outputs.

2

Add asynchronous reset logic

Inside the module, add an always block that is sensitive to posedge clk and posedge reset. This block will handle the asynchronous reset.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Hint

Use always @(posedge clk or posedge reset) to detect clock and reset changes.

3

Implement reset and data capture behavior

Inside the always block, write an if statement that sets q to 0 when reset is high. Otherwise, set q to d on the rising edge of clk.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Your code here
    end else begin
        // Your code here
    end
end

endmodule

Hint

Use non-blocking assignments <= to update q.

4

Test the D flip-flop output

Add a initial block to simulate the flip-flop behavior. Initialize reset to 1, then 0, and toggle clk while changing d. Use $display to print q after each clock edge.

Verilog

module d_flip_flop(input d, input clk, input reset, output reg q);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

initial begin
    // Your code here
end

Hint

Use initial block and $display to simulate and print values.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic