D flip-flop with asynchronous reset in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the module with inputs and outputs.

Verilog

module dff_async_reset(input clk, input rst_n, input [1], output reg q);

Drag options to blanks, or click blank then click option'

Ad

Bq

Cclk

Drst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset as data input

Using output signal name as input

The input data signal is named d in a D flip-flop.

2fill in blank

medium

Complete the sensitivity list for the always block to include clock and asynchronous reset.

Verilog

always @(negedge [1] or posedge clk) begin

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Arst_n

Bnegedge rst_n

Cposedge rst_n

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge for active low reset

Using clock edge instead of reset edge

The asynchronous reset triggers on the negative edge of rst_n.

3fill in blank

hard

Fix the error in the reset condition to correctly reset output q to 0.

Verilog

if ([1] == 1'b0) q <= 1'b0;

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Aclk

Bd

Crst_n

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or data signal in reset condition

Using output signal q in condition

The reset signal rst_n is active low, so when it is 0, q resets to 0.

4fill in blank

hard

Fill the blank to assign q the input d on clock rising edge when reset is inactive.

Verilog

else begin
  q <= [1];
end

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Ad

Bq

Crst_n

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning q to itself

Using reset or clock signals as data

On clock rising edge, q takes the value of d.

5fill in blank

hard

Fill all three blanks to complete the always block with asynchronous reset and data assignment.

Verilog

always @([1] or posedge [2]) begin
  if ([3] == 1'b0)
    q <= 1'b0;
  else
    q <= d;
end

Drag options to blanks, or click blank then click option'

Anegedge rst_n

Bclk

Crst_n

Dposedge rst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using positive edge for active low reset

Mixing clock and reset signals in conditions

The always block triggers on negative edge of reset and positive edge of clock. The reset signal rst_n is active low.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic