D flip-flop with asynchronous reset in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the module with inputs and outputs.

Verilog

module dff_async_reset(input clk, input rst_n, input [1], output reg q);

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Ad

Bq

Cclk

Drst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset as data input

Using output signal name as input

The input data signal is named d in a D flip-flop.

2fill in blank

medium

Complete the sensitivity list for the always block to include clock and asynchronous reset.

Verilog

always @(negedge [1] or posedge clk) begin

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Arst_n

Bnegedge rst_n

Cposedge rst_n

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge for active low reset

Using clock edge instead of reset edge

The asynchronous reset triggers on the negative edge of rst_n.

3fill in blank

hard

Fix the error in the reset condition to correctly reset output q to 0.

Verilog

if ([1] == 1'b0) q <= 1'b0;

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Aclk

Bd

Crst_n

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or data signal in reset condition

Using output signal q in condition

The reset signal rst_n is active low, so when it is 0, q resets to 0.

4fill in blank

hard

Fill the blank to assign q the input d on clock rising edge when reset is inactive.

Verilog

else begin
  q <= [1];
end

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Bq

Crst_n

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning q to itself

Using reset or clock signals as data

On clock rising edge, q takes the value of d.

5fill in blank

hard

Fill all three blanks to complete the always block with asynchronous reset and data assignment.

Verilog

always @([1] or posedge [2]) begin
  if ([3] == 1'b0)
    q <= 1'b0;
  else
    q <= d;
end

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Anegedge rst_n

Bclk

Crst_n

Dposedge rst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using positive edge for active low reset

Mixing clock and reset signals in conditions

The always block triggers on negative edge of reset and positive edge of clock. The reset signal rst_n is active low.