D flip-flop with asynchronous reset in Verilog - Time & Space Complexity
We want to understand how the time needed to run a D flip-flop with asynchronous reset changes as inputs change.
Specifically, how does the circuit's behavior scale with input signals over time?
Analyze the time complexity of the following code snippet.
module dff_async_reset (
input wire clk,
input wire rst_n,
input wire d,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 1'b0;
else
q <= d;
end
endmodule
This code models a D flip-flop that updates its output on the clock's rising edge or resets immediately when reset is low.
Identify the loops, recursion, array traversals that repeat.
- Primary operation: The flip-flop updates output on every clock cycle or reset event.
- How many times: Once per clock cycle or reset signal change, repeating continuously as the clock runs.
Each clock cycle triggers one update, so the number of operations grows directly with the number of clock cycles.
| Input Size (n) | Approx. Operations |
|---|---|
| 10 clock cycles | 10 updates |
| 100 clock cycles | 100 updates |
| 1000 clock cycles | 1000 updates |
Pattern observation: The operations increase linearly as the number of clock cycles increases.
Time Complexity: O(n)
This means the work done grows in a straight line with the number of clock cycles or reset events.
[X] Wrong: "The flip-flop updates multiple times per clock cycle, so complexity is higher."
[OK] Correct: The flip-flop only updates once per clock edge or reset event, so operations do not multiply within a single cycle.
Understanding how hardware elements like flip-flops behave over time helps you reason about timing and performance in digital designs.
"What if we added a synchronous reset instead of asynchronous? How would the time complexity change?"