D flip-flop with asynchronous reset in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop with asynchronous reset

What is the output Q after the following Verilog code runs for one clock cycle if reset is asserted asynchronously?

Verilog

module dff_async_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 1'b0;
    else
      q <= d;
  end
endmodule

// Initial state: q = 0
// Inputs at posedge clk: reset = 1, d = 1

A Q = 0

B Q = 1

C Q retains previous value

D Q toggles

💡 Hint

Remember asynchronous reset overrides the clocked data input.

When reset is asserted (high) asynchronously, the output Q is immediately set to 0 regardless of the clock or data input.

🧠 Conceptual

intermediate

Understanding sensitivity list in D flip-flop with async reset

Which signals must be included in the sensitivity list of a D flip-flop with asynchronous reset in Verilog?

A Clock, reset, and data signals

B Only the clock signal

C Only the reset signal

D Both clock and reset signals

💡 Hint

Think about what triggers the flip-flop to update output.

The flip-flop output updates on the rising edge of the clock or the rising edge of the asynchronous reset, so both must be in the sensitivity list.

🔧 Debug

advanced

Identify the error in this D flip-flop with async reset code

What error will occur when compiling this Verilog code for a D flip-flop with asynchronous reset? module dff(input clk, input reset, input d, output reg q); always @(posedge clk or reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule

A No error, code compiles and works correctly

B Runtime error: q never updates

C Syntax error: sensitivity list missing edge specification for reset

D Synthesis warning: asynchronous reset not supported

💡 Hint

Check how edges are specified in sensitivity lists.

The sensitivity list must specify edges for asynchronous signals. 'reset' alone is invalid; it should be 'posedge reset' or 'negedge reset'.

📝 Syntax

advanced

Correct asynchronous reset implementation

Which of the following Verilog code snippets correctly implements a positive-edge triggered D flip-flop with an active-high asynchronous reset?

A

always @(posedge clk or negedge reset) begin
  if (!reset)
    q <= 1'b0;
  else
    q <= d;
end

B

always @(posedge clk or posedge reset) begin
  if (reset == 1'b1)
    q <= 1'b0;
  else
    q <= d;
end

C

always @(posedge clk or reset) begin
  if (reset)
    q <= 1'b0;
  else
    q <= d;
end

D

always @(posedge clk) begin
  if (reset)
    q <= 1'b0;
  else
    q <= d;
end

💡 Hint

Asynchronous reset must be in sensitivity list with edge specified.

Option B correctly uses 'posedge reset' in sensitivity list and checks reset active high inside the block.

🚀 Application

expert

Number of clock cycles to clear output with async reset

Given a D flip-flop with asynchronous reset implemented as below, if reset is asserted high for 3 clock cycles and then deasserted, how many clock cycles after reset deassertion will it take for Q to reflect the input D? module dff(input clk, input reset, input d, output reg q); always @(posedge clk or posedge reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule

A 1 clock cycle after reset deassertion

B 3 clock cycles after reset deassertion

C Q never updates after reset

D Immediately at reset deassertion

💡 Hint

Think about when Q updates relative to clock edges and reset signal.

Q is cleared immediately when reset is high. After reset goes low, Q updates on the next rising clock edge, so 1 clock cycle delay.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic