D flip-flop with asynchronous reset in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of D flip-flop with asynchronous reset

What is the output Q after the following Verilog code runs for one clock cycle if reset is asserted asynchronously?

Verilog

module dff_async_reset(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 1'b0;
    else
      q <= d;
  end
endmodule

// Initial state: q = 0
// Inputs at posedge clk: reset = 1, d = 1

A Q = 0

B Q = 1

C Q retains previous value

D Q toggles

💡 Hint

Remember asynchronous reset overrides the clocked data input.

When reset is asserted (high) asynchronously, the output Q is immediately set to 0 regardless of the clock or data input.

🧠 Conceptual

intermediate

Understanding sensitivity list in D flip-flop with async reset

Which signals must be included in the sensitivity list of a D flip-flop with asynchronous reset in Verilog?

A Clock, reset, and data signals

B Only the clock signal

C Only the reset signal

D Both clock and reset signals

💡 Hint

Think about what triggers the flip-flop to update output.

The flip-flop output updates on the rising edge of the clock or the rising edge of the asynchronous reset, so both must be in the sensitivity list.

🔧 Debug

advanced

Identify the error in this D flip-flop with async reset code

What error will occur when compiling this Verilog code for a D flip-flop with asynchronous reset? module dff(input clk, input reset, input d, output reg q); always @(posedge clk or reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule

A No error, code compiles and works correctly

B Runtime error: q never updates

C Syntax error: sensitivity list missing edge specification for reset

D Synthesis warning: asynchronous reset not supported

💡 Hint

Check how edges are specified in sensitivity lists.

The sensitivity list must specify edges for asynchronous signals. 'reset' alone is invalid; it should be 'posedge reset' or 'negedge reset'.

📝 Syntax

advanced

Correct asynchronous reset implementation

Which of the following Verilog code snippets correctly implements a positive-edge triggered D flip-flop with an active-high asynchronous reset?

A

always @(posedge clk or negedge reset) begin
  if (!reset)
    q <= 1'b0;
  else
    q <= d;
end

B

always @(posedge clk or posedge reset) begin
  if (reset == 1'b1)
    q <= 1'b0;
  else
    q <= d;
end

C

always @(posedge clk or reset) begin
  if (reset)
    q <= 1'b0;
  else
    q <= d;
end

D

always @(posedge clk) begin
  if (reset)
    q <= 1'b0;
  else
    q <= d;
end

💡 Hint

Asynchronous reset must be in sensitivity list with edge specified.

Option B correctly uses 'posedge reset' in sensitivity list and checks reset active high inside the block.

🚀 Application

expert

Number of clock cycles to clear output with async reset

Given a D flip-flop with asynchronous reset implemented as below, if reset is asserted high for 3 clock cycles and then deasserted, how many clock cycles after reset deassertion will it take for Q to reflect the input D? module dff(input clk, input reset, input d, output reg q); always @(posedge clk or posedge reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule

A 1 clock cycle after reset deassertion

B 3 clock cycles after reset deassertion

C Q never updates after reset

D Immediately at reset deassertion

💡 Hint

Think about when Q updates relative to clock edges and reset signal.

Q is cleared immediately when reset is high. After reset goes low, Q updates on the next rising clock edge, so 1 clock cycle delay.