D flip-flop with asynchronous reset in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a D flip-flop with asynchronous reset?

A D flip-flop with asynchronous reset is a memory element that stores the input value (D) on the rising edge of the clock, but can be reset to 0 immediately when the reset signal is active, regardless of the clock.

beginner

In Verilog, how do you describe an asynchronous reset in a D flip-flop?

You include the reset signal in the sensitivity list with the clock and use an if statement to check if reset is active before checking the clock edge.

intermediate

Why is asynchronous reset useful in digital circuits?

It allows the circuit to be reset immediately without waiting for a clock edge, which is helpful for quickly initializing or clearing the state.

beginner

What happens if the asynchronous reset is active in a D flip-flop?

The output Q is forced to 0 immediately, ignoring the clock and input D until reset is deactivated.

beginner

Write the sensitivity list for a D flip-flop with asynchronous reset in Verilog.

always @(posedge clk or posedge reset)

What does the 'asynchronous reset' in a D flip-flop mean?

A Reset happens immediately, ignoring the clock

B Reset happens only on the clock's rising edge

C Reset happens only on the clock's falling edge

D Reset happens after a delay from the clock edge

Asynchronous reset means the flip-flop resets immediately when the reset signal is active, without waiting for the clock.

In Verilog, which signals should be in the sensitivity list for a D flip-flop with asynchronous reset?

A clk and reset

B clk only

C reset only

D clk, reset, and D

The sensitivity list must include clk and reset to detect changes on either signal.

What is the output Q when asynchronous reset is active?

A Q toggles

B Q holds its previous value

C Q is set to 0 immediately

D Q follows input D

When reset is active, Q is forced to 0 immediately.

Which Verilog statement correctly checks for asynchronous reset inside an always block?

A if (clk) Q <= D;

B if (reset) Q <= 0;

C if (posedge reset) Q <= 0;

D if (reset == 0) Q <= 0;

Inside the always block, you check if reset is active with if (reset) to set Q to 0.

What is the main difference between synchronous and asynchronous reset?

A Both reset types wait for clock edge

B Synchronous reset acts immediately; asynchronous reset waits for clock edge

C Both reset types act immediately

D Asynchronous reset acts immediately; synchronous reset waits for clock edge

Asynchronous reset forces output immediately; synchronous reset waits for the clock edge.

Explain how a D flip-flop with asynchronous reset works and why it is useful.

Think about how reset affects the output regardless of the clock.

Write a simple Verilog always block for a D flip-flop with asynchronous reset.

Include reset in sensitivity list and check reset first inside the block.