D flip-flop with asynchronous reset in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a D flip-flop with asynchronous reset?

A D flip-flop with asynchronous reset is a memory element that stores the input value (D) on the rising edge of the clock, but can be reset to 0 immediately when the reset signal is active, regardless of the clock.

beginner

In Verilog, how do you describe an asynchronous reset in a D flip-flop?

You include the reset signal in the sensitivity list with the clock and use an if statement to check if reset is active before checking the clock edge.

intermediate

Why is asynchronous reset useful in digital circuits?

It allows the circuit to be reset immediately without waiting for a clock edge, which is helpful for quickly initializing or clearing the state.

beginner

What happens if the asynchronous reset is active in a D flip-flop?

The output Q is forced to 0 immediately, ignoring the clock and input D until reset is deactivated.

beginner

Write the sensitivity list for a D flip-flop with asynchronous reset in Verilog.

always @(posedge clk or posedge reset)

What does the 'asynchronous reset' in a D flip-flop mean?

A Reset happens immediately, ignoring the clock

B Reset happens only on the clock's rising edge

C Reset happens only on the clock's falling edge

D Reset happens after a delay from the clock edge

Asynchronous reset means the flip-flop resets immediately when the reset signal is active, without waiting for the clock.

In Verilog, which signals should be in the sensitivity list for a D flip-flop with asynchronous reset?

A clk and reset

B clk only

C reset only

D clk, reset, and D

The sensitivity list must include clk and reset to detect changes on either signal.

What is the output Q when asynchronous reset is active?

A Q toggles

B Q holds its previous value

C Q is set to 0 immediately

D Q follows input D

When reset is active, Q is forced to 0 immediately.

Which Verilog statement correctly checks for asynchronous reset inside an always block?

A if (clk) Q <= D;

B if (reset) Q <= 0;

C if (posedge reset) Q <= 0;

D if (reset == 0) Q <= 0;

Inside the always block, you check if reset is active with if (reset) to set Q to 0.

What is the main difference between synchronous and asynchronous reset?

A Both reset types wait for clock edge

B Synchronous reset acts immediately; asynchronous reset waits for clock edge

C Both reset types act immediately

D Asynchronous reset acts immediately; synchronous reset waits for clock edge

Asynchronous reset forces output immediately; synchronous reset waits for the clock edge.

Explain how a D flip-flop with asynchronous reset works and why it is useful.

Think about how reset affects the output regardless of the clock.

Write a simple Verilog always block for a D flip-flop with asynchronous reset.

Include reset in sensitivity list and check reset first inside the block.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic