Always block sensitivity list in Verilog - Step-by-Step Execution

Concept Flow - Always block sensitivity list

Start simulation

↓

Event occurs on signal in sensitivity list?

Yes↓

Execute always block statements

↓

Wait for next event

No↓

Idle, no execution

↩Back to event wait

The always block runs only when a signal in its sensitivity list changes, then executes its statements and waits for the next event.

Execution Sample

Verilog

always @(posedge clk or negedge reset) begin
  if (!reset)
    q <= 0;
  else
    q <= d;
end

This always block triggers on clock rising edge or reset falling edge to update q.

Execution Table

Step	Event	Sensitivity List Match?	Action	q Value
1	reset falls from 1 to 0	Yes (negedge reset)	q <= 0	0
2	clk rises from 0 to 1	Yes (posedge clk)	q <= d (assume d=1)	1
3	clk stays at 1	No	No action	1
4	reset rises from 0 to 1	No	No action	1
5	clk rises from 0 to 1	Yes (posedge clk)	q <= d (assume d=0)	0
6	No event	No	No action	0

💡 No further events on sensitivity list signals, always block idle.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 5	Final
q	X (unknown)	0	1	0	0
clk	0	0	1	1	1
reset	1	0	0	1	1
d	Assumed 1	1	1	0	0

Key Moments - 3 Insights

Why does the always block not run when clk stays at 1 (Step 3)?

Because the sensitivity list triggers only on posedge clk or negedge reset, no change means no trigger (see execution_table Step 3).

What happens if a signal not in the sensitivity list changes?

The always block does not run since only signals in the sensitivity list cause execution (see no action in Steps 3 and 4).

Why include both posedge clk and negedge reset in sensitivity list?

To react immediately to reset going low and clock rising edges, ensuring synchronous and asynchronous control (see Step 1 and Step 2).

Visual Quiz - 3 Questions

Look at the execution table, what is the value of q after Step 2?

A 0

B 1

C X (unknown)

D d (input value)

💡 Hint

Check the 'q Value' column at Step 2 in the execution_table.

At which step does the always block execute because of negedge reset?

A Step 4

B Step 2

C Step 1

D Step 5

💡 Hint

Look for 'reset falls from 1 to 0' event in execution_table.

If the sensitivity list only had posedge clk, what would happen at Step 1?

A Always block does not run, q unchanged

B Always block runs but q unchanged

C Always block runs and q <= 0

D Simulation error

💡 Hint

Step 1 event is negedge reset, which would not trigger if sensitivity list lacks reset.

Concept Snapshot

always @(sensitivity_list) begin
  // statements
end

- Runs only when a signal in sensitivity_list changes
- Use posedge/negedge for edge-triggered events
- Sensitivity list controls when block executes
- Missing signals means block won't react to their changes

Full Transcript

An always block in Verilog runs its code only when a signal in its sensitivity list changes. For example, if the sensitivity list is posedge clk or negedge reset, the block runs when the clock rises or reset falls. Inside, it can update variables like q. If no signal in the list changes, the block does not run. This behavior ensures efficient and correct hardware simulation and design.