Always block sensitivity list in Verilog - Step-by-Step Execution

Concept Flow - Always block sensitivity list

Start simulation

↓

Event occurs on signal in sensitivity list?

Yes↓

Execute always block statements

↓

Wait for next event

No↓

Idle, no execution

↩Back to event wait

The always block runs only when a signal in its sensitivity list changes, then executes its statements and waits for the next event.

Execution Sample

Verilog

always @(posedge clk or negedge reset) begin
  if (!reset)
    q <= 0;
  else
    q <= d;
end

This always block triggers on clock rising edge or reset falling edge to update q.

Execution Table

Step	Event	Sensitivity List Match?	Action	q Value
1	reset falls from 1 to 0	Yes (negedge reset)	q <= 0	0
2	clk rises from 0 to 1	Yes (posedge clk)	q <= d (assume d=1)	1
3	clk stays at 1	No	No action	1
4	reset rises from 0 to 1	No	No action	1
5	clk rises from 0 to 1	Yes (posedge clk)	q <= d (assume d=0)	0
6	No event	No	No action	0

💡 No further events on sensitivity list signals, always block idle.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 5	Final
q	X (unknown)	0	1	0	0
clk	0	0	1	1	1
reset	1	0	0	1	1
d	Assumed 1	1	1	0	0

Key Moments - 3 Insights

Why does the always block not run when clk stays at 1 (Step 3)?

Because the sensitivity list triggers only on posedge clk or negedge reset, no change means no trigger (see execution_table Step 3).

What happens if a signal not in the sensitivity list changes?

The always block does not run since only signals in the sensitivity list cause execution (see no action in Steps 3 and 4).

Why include both posedge clk and negedge reset in sensitivity list?

To react immediately to reset going low and clock rising edges, ensuring synchronous and asynchronous control (see Step 1 and Step 2).

Visual Quiz - 3 Questions

Look at the execution table, what is the value of q after Step 2?

A 0

B 1

C X (unknown)

D d (input value)

💡 Hint

Check the 'q Value' column at Step 2 in the execution_table.

At which step does the always block execute because of negedge reset?

A Step 4

B Step 2

C Step 1

D Step 5

💡 Hint

Look for 'reset falls from 1 to 0' event in execution_table.

If the sensitivity list only had posedge clk, what would happen at Step 1?

A Always block does not run, q unchanged

B Always block runs but q unchanged

C Always block runs and q <= 0

D Simulation error

💡 Hint

Step 1 event is negedge reset, which would not trigger if sensitivity list lacks reset.

Concept Snapshot

always @(sensitivity_list) begin
  // statements
end

- Runs only when a signal in sensitivity_list changes
- Use posedge/negedge for edge-triggered events
- Sensitivity list controls when block executes
- Missing signals means block won't react to their changes

Full Transcript

An always block in Verilog runs its code only when a signal in its sensitivity list changes. For example, if the sensitivity list is posedge clk or negedge reset, the block runs when the clock rises or reset falls. Inside, it can update variables like q. If no signal in the list changes, the block does not run. This behavior ensures efficient and correct hardware simulation and design.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list