Always block sensitivity list in Verilog - Mini Project: Build & Apply

Always Block Sensitivity List

📖 Scenario: You are designing a simple digital circuit in Verilog that reacts to changes in input signals. To do this correctly, you need to understand how to write an always block with the proper sensitivity list so your circuit updates at the right times.

🎯 Goal: Build a Verilog module with an always block that triggers whenever either input a or input b changes, and outputs their sum on sum.

📋 What You'll Learn

Create a module named adder with inputs a and b and output sum

Use an always block with a sensitivity list that includes a and b

Inside the always block, assign sum the value of a + b

Use non-blocking assignment <= inside the always block

💡 Why This Matters

🌍 Real World

Digital circuits often need to update outputs when inputs change. Using the correct sensitivity list in an always block ensures the circuit behaves as expected.

💼 Career

Understanding always blocks and sensitivity lists is essential for hardware design engineers working with Verilog or other hardware description languages.

1

Create the module and inputs/outputs

Write a Verilog module named adder with inputs a and b as 4-bit wires, and output sum as a 5-bit reg.

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

// Your code here

endmodule

Need a hint?

Define the module and declare inputs and outputs exactly as specified.

2

Add the always block with sensitivity list

Inside the adder module, add an always block with sensitivity list @(a or b).

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

always @(a or b) begin
    // Your code here
end

endmodule

Need a hint?

Use always @(a or b) to trigger the block when a or b changes.

3

Assign sum inside the always block

Inside the always block, assign sum the value of a + b using non-blocking assignment <=.

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

always @(a or b) begin
    // Your code here
end

endmodule

Need a hint?

Use sum <= a + b; inside the always block.

4

Display the module code

Print the complete adder module code.

Verilog

// Your code here

Need a hint?

Use $display statements to print the module code lines.