Always block sensitivity list in Verilog - Mini Project: Build & Apply

Always Block Sensitivity List

📖 Scenario: You are designing a simple digital circuit in Verilog that reacts to changes in input signals. To do this correctly, you need to understand how to write an always block with the proper sensitivity list so your circuit updates at the right times.

🎯 Goal: Build a Verilog module with an always block that triggers whenever either input a or input b changes, and outputs their sum on sum.

📋 What You'll Learn

Create a module named adder with inputs a and b and output sum

Use an always block with a sensitivity list that includes a and b

Inside the always block, assign sum the value of a + b

Use non-blocking assignment <= inside the always block

💡 Why This Matters

🌍 Real World

Digital circuits often need to update outputs when inputs change. Using the correct sensitivity list in an always block ensures the circuit behaves as expected.

💼 Career

Understanding always blocks and sensitivity lists is essential for hardware design engineers working with Verilog or other hardware description languages.

1

Create the module and inputs/outputs

Write a Verilog module named adder with inputs a and b as 4-bit wires, and output sum as a 5-bit reg.

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

// Your code here

endmodule

Hint

Define the module and declare inputs and outputs exactly as specified.

2

Add the always block with sensitivity list

Inside the adder module, add an always block with sensitivity list @(a or b).

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

always @(a or b) begin
    // Your code here
end

endmodule

Hint

Use always @(a or b) to trigger the block when a or b changes.

3

Assign sum inside the always block

Inside the always block, assign sum the value of a + b using non-blocking assignment <=.

Verilog

module adder(input wire [3:0] a, input wire [3:0] b, output reg [4:0] sum);

always @(a or b) begin
    // Your code here
end

endmodule

Hint

Use sum <= a + b; inside the always block.

4

Display the module code

Print the complete adder module code.

Verilog

// Your code here

Hint

Use $display statements to print the module code lines.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list