Always block sensitivity list in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of the sensitivity list in a Verilog always block?

The sensitivity list tells the always block which signals to watch. When any signal in the list changes, the block runs its code.

intermediate

What happens if you leave out a signal from the sensitivity list in an always block?

The always block will not run when that signal changes, which can cause incorrect or unexpected behavior in your design.

beginner

How do you write an always block that triggers on any change of signals a, b, or c?

Use: always @(a or b or c) begin ... end. This means the block runs when a, b, or c changes.

intermediate

What is the difference between using 'always @*' and listing signals explicitly in the sensitivity list?

'always @*' automatically includes all signals read inside the block, reducing errors from missing signals. Explicit lists require manual updates.

intermediate

Why is it important to use the correct sensitivity list in combinational logic always blocks?

Because incorrect sensitivity lists can cause simulation mismatches and hardware bugs, as the block may not update when inputs change.

What does the sensitivity list in a Verilog always block specify?

A Signals that are ignored by the block

B Signals that trigger the block to run when they change

C Signals that the block will output

D The clock frequency

The sensitivity list tells the always block which signals to watch for changes to run the block.

Which of the following is the correct way to write an always block sensitive to signals a and b?

A always @(a or b)

B always @(a and b)

C always @(posedge a or posedge b)

D always @(a, b)

The sensitivity list uses 'or' to list signals that trigger the block when any changes.

What does 'always @*' mean in Verilog?

A The block runs only on clock edges

B The block runs only once

C The block never runs

D The block runs when any signal it reads changes

'always @*' automatically includes all signals read inside the block in the sensitivity list.

What is a common problem if a signal is missing from the sensitivity list in a combinational always block?

A The block will ignore all signals

B The block will run twice as fast

C The block might not update when that signal changes

D The block will cause a syntax error

Missing signals cause the block to not run when those signals change, leading to incorrect behavior.

Why is 'always @*' recommended for combinational logic?

A It reduces errors by automatically including all input signals

B It makes the code run faster

C It disables the always block

D It only triggers on clock edges

'always @*' helps avoid missing signals in the sensitivity list, making code safer and easier to maintain.

Explain what the sensitivity list in a Verilog always block does and why it is important.

Think about what happens when a signal changes and how the always block reacts.

Describe the difference between using an explicit sensitivity list and 'always @*' in Verilog.

Consider how each method handles signals inside the block.