Always block sensitivity list in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of the sensitivity list in a Verilog always block?

The sensitivity list tells the always block which signals to watch. When any signal in the list changes, the block runs its code.

intermediate

What happens if you leave out a signal from the sensitivity list in an always block?

The always block will not run when that signal changes, which can cause incorrect or unexpected behavior in your design.

beginner

How do you write an always block that triggers on any change of signals a, b, or c?

Use: always @(a or b or c) begin ... end. This means the block runs when a, b, or c changes.

intermediate

What is the difference between using 'always @*' and listing signals explicitly in the sensitivity list?

'always @*' automatically includes all signals read inside the block, reducing errors from missing signals. Explicit lists require manual updates.

intermediate

Why is it important to use the correct sensitivity list in combinational logic always blocks?

Because incorrect sensitivity lists can cause simulation mismatches and hardware bugs, as the block may not update when inputs change.

What does the sensitivity list in a Verilog always block specify?

A Signals that are ignored by the block

B Signals that trigger the block to run when they change

C Signals that the block will output

D The clock frequency

The sensitivity list tells the always block which signals to watch for changes to run the block.

Which of the following is the correct way to write an always block sensitive to signals a and b?

A always @(a or b)

B always @(a and b)

C always @(posedge a or posedge b)

D always @(a, b)

The sensitivity list uses 'or' to list signals that trigger the block when any changes.

What does 'always @*' mean in Verilog?

A The block runs only on clock edges

B The block runs only once

C The block never runs

D The block runs when any signal it reads changes

'always @*' automatically includes all signals read inside the block in the sensitivity list.

What is a common problem if a signal is missing from the sensitivity list in a combinational always block?

A The block will ignore all signals

B The block will run twice as fast

C The block might not update when that signal changes

D The block will cause a syntax error

Missing signals cause the block to not run when those signals change, leading to incorrect behavior.

Why is 'always @*' recommended for combinational logic?

A It reduces errors by automatically including all input signals

B It makes the code run faster

C It disables the always block

D It only triggers on clock edges

'always @*' helps avoid missing signals in the sensitivity list, making code safer and easier to maintain.

Explain what the sensitivity list in a Verilog always block does and why it is important.

Think about what happens when a signal changes and how the always block reacts.

Describe the difference between using an explicit sensitivity list and 'always @*' in Verilog.

Consider how each method handles signals inside the block.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list