Always block sensitivity list in Verilog - Time & Space Complexity

Time Complexity: Always block sensitivity list

O(n)

Understanding Time Complexity

We want to understand how the execution time of an always block changes as the inputs it watches change.

How does the number of operations grow when signals in the sensitivity list change?

Scenario Under Consideration

Analyze the time complexity of the following Verilog always block.

always @(posedge clk or negedge reset_n) begin
  if (!reset_n) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

This block increments a counter on each clock rising edge, or resets it when reset is low.

Identify Repeating Operations

Look for repeated actions triggered by signals.

• Primary operation: The block runs once every time the clock rises or reset falls.
• How many times: It runs once per clock cycle or reset event, not continuously.

How Execution Grows With Input

The block runs only when signals in the sensitivity list change.

Input Size (number of signal changes)	Approx. Operations
10 clock cycles	10 executions
100 clock cycles	100 executions
1000 clock cycles	1000 executions

Pattern observation: The number of executions grows linearly with the number of signal changes.

Final Time Complexity

Time Complexity: O(n)

This means the block runs once for each input event, so the total work grows directly with the number of events.

Common Mistake

[X] Wrong: "The always block runs continuously and uses a lot of time even if inputs don't change."

[OK] Correct: The always block only runs when signals in its sensitivity list change, so it does not waste time running when inputs are stable.

Interview Connect

Understanding how always blocks trigger helps you write efficient hardware code and explain timing behavior clearly in interviews.

Self-Check

"What if we add more signals to the sensitivity list? How would that affect the time complexity?"