Always block sensitivity list in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to trigger the always block on the positive edge of clk.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aclk

Bposedge clk

Cd

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using just 'clk' instead of 'posedge clk' causes the block to trigger on any change.

Using 'negedge clk' triggers on the falling edge, which might not be intended.

The always block should be sensitive to the positive edge of the clock signal clk to update q correctly.

2fill in blank

medium

Complete the code to trigger the always block on the negative edge of reset.

Verilog

always @([1]) begin
  if (!reset_n) begin
    q <= 0;
  end
end

Drag options to blanks, or click blank then click option'

Anegedge reset_n

Bposedge reset_n

Creset_n

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge reset_n' triggers on the wrong edge.

Using just 'reset_n' triggers on any change, causing unintended resets.

The always block should be sensitive to the negative edge of the active-low reset signal reset_n to reset q properly.

3fill in blank

hard

Fix the error in the sensitivity list to trigger on both posedge clk and negedge reset_n.

Verilog

always @([1]) begin
  if (!reset_n) q <= 0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or negedge reset_n

Bclk or reset_n

Cnegedge clk or negedge reset_n

Dposedge clk or posedge reset_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset_n triggers reset on the wrong edge.

Using just 'clk or reset_n' triggers on any change, causing glitches.

The always block should trigger on the positive edge of clk and the negative edge of reset_n to handle synchronous data and asynchronous reset.

4fill in blank

hard

Fill both blanks to create an always block sensitive to posedge clk and posedge enable.

Verilog

always @([1] or [2]) begin
  if (enable) q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge clk

Cposedge enable

Dnegedge enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge for clock or enable when posedge is required.

Missing one of the signals in the sensitivity list.

The always block triggers on the positive edges of both clk and enable signals.

5fill in blank

hard

Fill all three blanks to create an always block sensitive to posedge clk, negedge reset_n, and posedge set.

Verilog

always @([1] or [2] or [3]) begin
  if (!reset_n) q <= 0;
  else if (set) q <= 1;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge reset_n

Cposedge set

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset_n instead of negedge.

Using negedge set instead of posedge.

Missing one of the signals in the sensitivity list.

The always block triggers on the positive edge of clk, the negative edge of reset_n, and the positive edge of set to handle synchronous data, asynchronous reset, and asynchronous set.