Always block sensitivity list in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to trigger the always block on the positive edge of clk.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aclk

Bposedge clk

Cd

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using just 'clk' instead of 'posedge clk' causes the block to trigger on any change.

Using 'negedge clk' triggers on the falling edge, which might not be intended.

The always block should be sensitive to the positive edge of the clock signal clk to update q correctly.

2fill in blank

medium

Complete the code to trigger the always block on the negative edge of reset.

Verilog

always @([1]) begin
  if (!reset_n) begin
    q <= 0;
  end
end

Drag options to blanks, or click blank then click option'

Anegedge reset_n

Bposedge reset_n

Creset_n

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge reset_n' triggers on the wrong edge.

Using just 'reset_n' triggers on any change, causing unintended resets.

The always block should be sensitive to the negative edge of the active-low reset signal reset_n to reset q properly.

3fill in blank

hard

Fix the error in the sensitivity list to trigger on both posedge clk and negedge reset_n.

Verilog

always @([1]) begin
  if (!reset_n) q <= 0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or negedge reset_n

Bclk or reset_n

Cnegedge clk or negedge reset_n

Dposedge clk or posedge reset_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset_n triggers reset on the wrong edge.

Using just 'clk or reset_n' triggers on any change, causing glitches.

The always block should trigger on the positive edge of clk and the negative edge of reset_n to handle synchronous data and asynchronous reset.

4fill in blank

hard

Fill both blanks to create an always block sensitive to posedge clk and posedge enable.

Verilog

always @([1] or [2]) begin
  if (enable) q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge clk

Cposedge enable

Dnegedge enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge for clock or enable when posedge is required.

Missing one of the signals in the sensitivity list.

The always block triggers on the positive edges of both clk and enable signals.

5fill in blank

hard

Fill all three blanks to create an always block sensitive to posedge clk, negedge reset_n, and posedge set.

Verilog

always @([1] or [2] or [3]) begin
  if (!reset_n) q <= 0;
  else if (set) q <= 1;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge reset_n

Cposedge set

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset_n instead of negedge.

Using negedge set instead of posedge.

Missing one of the signals in the sensitivity list.

The always block triggers on the positive edge of clk, the negative edge of reset_n, and the positive edge of set to handle synchronous data, asynchronous reset, and asynchronous set.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list