Always block sensitivity list in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of always block with posedge clock sensitivity

What is the output of the following Verilog code snippet when the clock rises?

Verilog

module test;
  reg clk = 0;
  reg [3:0] count = 0;
  always @(posedge clk) begin
    count <= count + 1;
  end
  initial begin
    #1 clk = 1;
    #1 clk = 0;
    #1 clk = 1;
    #1 clk = 0;
    #1 $display("Count: %d", count);
    $finish;
  end
endmodule

A Count: 2

B Count: 3

C Count: 0

D Count: 1

💡 Hint

Count increments on each rising edge of clk.

The always block triggers on posedge clk. The clock rises twice, so count increments twice from 0 to 2.

❓ Predict Output

intermediate

Output of always block with negedge reset sensitivity

What will be the value of q after the following code runs?

Verilog

module test;
  reg rst_n = 1;
  reg clk = 0;
  reg q = 0;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= 1;
  end
  initial begin
    #1 rst_n = 0;
    #1 rst_n = 1;
    #1 clk = 1;
    #1 clk = 0;
    #1 $display("q = %d", q);
    $finish;
  end
endmodule

A q = 0

B q = 1

C q = x (unknown)

D q = 2

💡 Hint

Reset is active low and asynchronous.

Reset is asserted low, setting q to 0. Then reset deasserts and clock rises, setting q to 1.

🔧 Debug

advanced

Identify error in always block sensitivity list

Which option shows the correct sensitivity list for a combinational always block that depends on inputs a and b?

Verilog

always @(a or b) begin
  y = a & b;
end

A always @(posedge a or posedge b)

B always @(a and b)

C always @(a or b)

D always @(posedge a and posedge b)

💡 Hint

Combinational blocks use level sensitivity, not edge sensitivity.

Combinational always blocks must list signals with 'or' to trigger on any change. Edge sensitivity (posedge/negedge) is for sequential logic.

📝 Syntax

advanced

Syntax error in always block sensitivity list

Which option will cause a syntax error in the always block sensitivity list?

A always @(clk posedge or rst_n negedge)

B always @(clk or rst_n)

C always @(posedge clk or negedge rst_n)

D always @(posedge clk and negedge rst_n)

💡 Hint

Sensitivity list keywords must come before signal names.

Option A reverses the order: 'clk posedge' is invalid syntax. The correct form is 'posedge clk'.

🚀 Application

expert

Number of triggers in always block sensitivity list

Given the following always block, how many times will it trigger during the simulation?

reg a = 0, b = 0, c = 0;
always @(a or b or c) begin
  // some logic
end
initial begin
  a = 1; b = 1; c = 1;
  #1 a = 0;
  #1 b = 0;
  #1 c = 0;
  #1 $finish;
end

A 1

B 4

C 3

D 6

💡 Hint

Count each change in a, b, and c that triggers the block.

The block triggers on any change of a, b, or c. Initial assignments change all three (3 triggers), then each #1 step changes one signal (3 more triggers), total 6.