Always block sensitivity list in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of always block with posedge clock sensitivity

What is the output of the following Verilog code snippet when the clock rises?

Verilog

module test;
  reg clk = 0;
  reg [3:0] count = 0;
  always @(posedge clk) begin
    count <= count + 1;
  end
  initial begin
    #1 clk = 1;
    #1 clk = 0;
    #1 clk = 1;
    #1 clk = 0;
    #1 $display("Count: %d", count);
    $finish;
  end
endmodule

A Count: 2

B Count: 3

C Count: 0

D Count: 1

💡 Hint

Count increments on each rising edge of clk.

The always block triggers on posedge clk. The clock rises twice, so count increments twice from 0 to 2.

❓ Predict Output

intermediate

Output of always block with negedge reset sensitivity

What will be the value of q after the following code runs?

Verilog

module test;
  reg rst_n = 1;
  reg clk = 0;
  reg q = 0;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= 1;
  end
  initial begin
    #1 rst_n = 0;
    #1 rst_n = 1;
    #1 clk = 1;
    #1 clk = 0;
    #1 $display("q = %d", q);
    $finish;
  end
endmodule

A q = 0

B q = 1

C q = x (unknown)

D q = 2

💡 Hint

Reset is active low and asynchronous.

Reset is asserted low, setting q to 0. Then reset deasserts and clock rises, setting q to 1.

🔧 Debug

advanced

Identify error in always block sensitivity list

Which option shows the correct sensitivity list for a combinational always block that depends on inputs a and b?

Verilog

always @(a or b) begin
  y = a & b;
end

A always @(posedge a or posedge b)

B always @(a and b)

C always @(a or b)

D always @(posedge a and posedge b)

💡 Hint

Combinational blocks use level sensitivity, not edge sensitivity.

Combinational always blocks must list signals with 'or' to trigger on any change. Edge sensitivity (posedge/negedge) is for sequential logic.

📝 Syntax

advanced

Syntax error in always block sensitivity list

Which option will cause a syntax error in the always block sensitivity list?

A always @(clk posedge or rst_n negedge)

B always @(clk or rst_n)

C always @(posedge clk or negedge rst_n)

D always @(posedge clk and negedge rst_n)

💡 Hint

Sensitivity list keywords must come before signal names.

Option A reverses the order: 'clk posedge' is invalid syntax. The correct form is 'posedge clk'.

🚀 Application

expert

Number of triggers in always block sensitivity list

Given the following always block, how many times will it trigger during the simulation?

reg a = 0, b = 0, c = 0;
always @(a or b or c) begin
  // some logic
end
initial begin
  a = 1; b = 1; c = 1;
  #1 a = 0;
  #1 b = 0;
  #1 c = 0;
  #1 $finish;
end

A 1

B 4

C 3

D 6

💡 Hint

Count each change in a, b, and c that triggers the block.

The block triggers on any change of a, b, or c. Initial assignments change all three (3 triggers), then each #1 step changes one signal (3 more triggers), total 6.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list