Why FSMs model sequential behavior in Verilog - Visual Breakdown

Concept Flow - Why FSMs model sequential behavior

Start: Initial State

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Input Received

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Evaluate Current State + Input

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Transition to Next State

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Output Based on State

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Wait for Next Clock Cycle

↩Back to Input Received

The FSM waits for inputs, checks current state and input, moves to the next state, produces output, then waits for the next clock cycle to repeat.

Execution Sample

Verilog

always @(posedge clk) begin
  case (state)
    IDLE: if (start) state <= RUN;
    RUN: if (stop) state <= IDLE;
  endcase
end

This code shows a simple FSM changing states on clock edges based on inputs.

Execution Table

Step	Clock Edge	Current State	Input (start/stop)	Next State	Output	Action
1	Rising	IDLE	start=0, stop=0	IDLE	Idle output	No start, stay IDLE
2	Rising	IDLE	start=1, stop=0	RUN	Run output	Start detected, move to RUN
3	Rising	RUN	start=0, stop=0	RUN	Run output	No stop, stay RUN
4	Rising	RUN	start=0, stop=1	IDLE	Idle output	Stop detected, move to IDLE
5	Rising	IDLE	start=0, stop=0	IDLE	Idle output	No start, stay IDLE

💡 FSM continues cycling on clock edges, changing states based on inputs.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
state	IDLE	IDLE	RUN	RUN	IDLE	IDLE
output	Idle output	Idle output	Run output	Run output	Idle output	Idle output

Key Moments - 2 Insights

Why does the FSM only change state on the clock's rising edge?

Because the FSM is synchronous, it updates state only at clock edges to keep behavior predictable and stable, as shown in execution_table steps where state changes happen only at 'Rising' clock edges.

Why does the FSM stay in the same state if inputs don't trigger a change?

The FSM checks inputs each clock cycle but only changes state if conditions are met; otherwise, it remains in the current state, as seen in steps 1 and 3 where inputs don't cause transitions.

Visual Quiz - 3 Questions

Look at the execution table, what is the state after step 2?

A IDLE

B RUN

C STOP

D START

💡 Hint

Check the 'Next State' column at step 2 in the execution_table.

At which step does the FSM transition back to IDLE?

A Step 3

B Step 2

C Step 4

D Step 5

💡 Hint

Look for 'Next State' changing to IDLE in the execution_table.

If the input 'start' is never 1, what will the FSM state be after step 5?

A IDLE

B STOP

C RUN

D Undefined

💡 Hint

Refer to variable_tracker for 'state' when 'start' remains 0.

Concept Snapshot

FSMs model sequential behavior by changing states only on clock edges.
They remember current state and input to decide next state.
Outputs depend on current state.
This makes FSMs perfect for step-by-step processes.
State changes are synchronous and predictable.

Full Transcript

Finite State Machines (FSMs) model sequential behavior by moving through states step-by-step on clock edges. At each rising clock edge, the FSM checks its current state and inputs, then decides the next state and output. If inputs don't trigger a change, the FSM stays in the same state. This synchronous update ensures predictable and stable behavior. The example code shows a simple FSM switching between IDLE and RUN states based on start and stop inputs. The execution table traces each clock cycle, showing state and output changes. This stepwise process is why FSMs are used to model sequential logic in hardware design.

Practice

1.

Why do FSMs (Finite State Machines) model sequential behavior effectively in Verilog?

easy

A. Because they execute all states simultaneously without memory.

B. Because they only use combinational logic without any clock.

C. Because they move through a series of states one after another, remembering past states.

D. Because they randomly change states without any order.

Solution

1. Step 1: Understand FSM state transitions

   FSMs move step-by-step through states, which models sequences of actions over time.

2. Step 2: Recognize memory role in FSMs

   FSMs remember the current state, so they know what to do next based on past states.

3. Final Answer:

   Because they move through a series of states one after another, remembering past states. -> Option C

4. Quick Check:

   FSMs use states and memory = Because they move through a series of states one after another, remembering past states. [OK]

Hint: FSMs remember past states to model sequences [OK]

Common Mistakes:

• Thinking FSMs run all states at once
• Confusing FSMs with purely combinational logic
• Assuming FSMs change states randomly

2.

Which Verilog code snippet correctly declares a state register for an FSM?

module fsm_example(clk, reset);
  input clk, reset;
  // Which line correctly declares the state register?
  // A) reg [1:0] state;
  // B) wire state;
  // C) integer state;
  // D) reg state = 0;
endmodule

easy

A. reg state = 0;

B. wire state;

C. integer state;

D. reg [1:0] state;

Solution

1. Step 1: Identify correct register declaration for FSM state

   FSM states are stored in registers, typically as a vector for multiple states, so reg [1:0] state; is correct.

2. Step 2: Eliminate incorrect options

   wire cannot store state, integer is not typical for FSM states, and reg state = 0; lacks bit width for multiple states.

3. Final Answer:

   reg [1:0] state; -> Option D

4. Quick Check:

   FSM state needs reg with bit width = reg [1:0] state; [OK]

Hint: FSM states need reg with bit width, not wire [OK]

Common Mistakes:

• Using wire instead of reg for state
• Not specifying bit width for multiple states
• Initializing reg in declaration (not synthesizable)

3.

What is the output of this FSM code snippet after 3 clock cycles if reset is 0 and initial state is 2'b00?

reg [1:0] state;
always @(posedge clk or posedge reset) begin
  if (reset) state <= 2'b00;
  else begin
    case(state)
      2'b00: state <= 2'b01;
      2'b01: state <= 2'b10;
      2'b10: state <= 2'b00;
      default: state <= 2'b00;
    endcase
  end
end
// What is state after 3 clock cycles?

medium

A. 2'b00

B. 2'b01

C. 2'b10

D. 2'b11

Solution

1. Step 1: Trace state transitions from initial state

   Start at 2'b00, cycle 1: state=2'b01, cycle 2: state=2'b10, cycle 3: state=2'b00.

2. Step 2: Confirm state after 3 cycles

   After 3 clock cycles, the FSM returns to 2'b00 as per the cycle defined.

3. Final Answer:

   2'b00 -> Option A

4. Quick Check:

   State cycles 00->01->10->00 = 2'b00 [OK]

Hint: Follow state changes step-by-step per clock [OK]

Common Mistakes:

• Forgetting initial state
• Counting reset as a clock cycle
• Misreading state transitions

4.

Identify the error in this FSM snippet that prevents correct sequential behavior:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state = 2'b01;
    2'b01: state = 2'b10;
    2'b10: state = 2'b00;
  endcase
end

medium

A. All of the above.

B. Missing reset condition to initialize state.

C. No default case in the case statement.

D. Using blocking assignment (=) instead of non-blocking (<=) inside always block.

Solution

1. Step 1: Check assignment type in sequential always block

   Blocking assignment (=) should be replaced with non-blocking (<=) for correct sequential logic.

2. Step 2: Check for reset and default case

   There is no reset to initialize state, and no default case to handle unexpected states.

3. Final Answer:

   All of the above. -> Option A

4. Quick Check:

   Blocking assignment + no reset + no default = All of the above. [OK]

Hint: Use <= in sequential blocks and always include reset [OK]

Common Mistakes:

• Using = instead of <= in always block
• Forgetting reset logic
• Ignoring default case in FSM

5.

You want to design an FSM in Verilog that controls a traffic light sequence: Green (G), Yellow (Y), Red (R), then back to Green. Which approach best models this sequential behavior?

hard

A. Use random state changes without memory to simulate traffic flow.

B. Use a state register with states G, Y, R and transition on clock edges remembering past state.

C. Use combinational logic only to set lights based on input switches.

D. Use multiple always blocks without a state register.

Solution

1. Step 1: Identify FSM role in traffic light control

   Traffic lights follow a fixed sequence, so an FSM with states for each light is ideal.

2. Step 2: Understand why state register and clock are needed

   The FSM uses a state register to remember current light and transitions on clock edges to next state.

3. Final Answer:

   Use a state register with states G, Y, R and transition on clock edges remembering past state. -> Option B

4. Quick Check:

   Sequential control with state memory = Use a state register with states G, Y, R and transition on clock edges remembering past state. [OK]

Hint: Model sequences with states and clocked transitions [OK]

Common Mistakes:

• Trying to use combinational logic only
• Ignoring state memory for sequence
• Using random or multiple always blocks without state