Why FSMs model sequential behavior in Verilog - Visual Breakdown

Concept Flow - Why FSMs model sequential behavior

Start: Initial State

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Input Received

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Evaluate Current State + Input

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Transition to Next State

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Output Based on State

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Wait for Next Clock Cycle

↩Back to Input Received

The FSM waits for inputs, checks current state and input, moves to the next state, produces output, then waits for the next clock cycle to repeat.

Execution Sample

Verilog

always @(posedge clk) begin
  case (state)
    IDLE: if (start) state <= RUN;
    RUN: if (stop) state <= IDLE;
  endcase
end

This code shows a simple FSM changing states on clock edges based on inputs.

Execution Table

Step	Clock Edge	Current State	Input (start/stop)	Next State	Output	Action
1	Rising	IDLE	start=0, stop=0	IDLE	Idle output	No start, stay IDLE
2	Rising	IDLE	start=1, stop=0	RUN	Run output	Start detected, move to RUN
3	Rising	RUN	start=0, stop=0	RUN	Run output	No stop, stay RUN
4	Rising	RUN	start=0, stop=1	IDLE	Idle output	Stop detected, move to IDLE
5	Rising	IDLE	start=0, stop=0	IDLE	Idle output	No start, stay IDLE

💡 FSM continues cycling on clock edges, changing states based on inputs.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
state	IDLE	IDLE	RUN	RUN	IDLE	IDLE
output	Idle output	Idle output	Run output	Run output	Idle output	Idle output

Key Moments - 2 Insights

Why does the FSM only change state on the clock's rising edge?

Because the FSM is synchronous, it updates state only at clock edges to keep behavior predictable and stable, as shown in execution_table steps where state changes happen only at 'Rising' clock edges.

Why does the FSM stay in the same state if inputs don't trigger a change?

The FSM checks inputs each clock cycle but only changes state if conditions are met; otherwise, it remains in the current state, as seen in steps 1 and 3 where inputs don't cause transitions.

Visual Quiz - 3 Questions

Look at the execution table, what is the state after step 2?

A IDLE

B RUN

C STOP

D START

💡 Hint

Check the 'Next State' column at step 2 in the execution_table.

At which step does the FSM transition back to IDLE?

A Step 3

B Step 2

C Step 4

D Step 5

💡 Hint

Look for 'Next State' changing to IDLE in the execution_table.

If the input 'start' is never 1, what will the FSM state be after step 5?

A IDLE

B STOP

C RUN

D Undefined

💡 Hint

Refer to variable_tracker for 'state' when 'start' remains 0.

Concept Snapshot

FSMs model sequential behavior by changing states only on clock edges.
They remember current state and input to decide next state.
Outputs depend on current state.
This makes FSMs perfect for step-by-step processes.
State changes are synchronous and predictable.

Full Transcript

Finite State Machines (FSMs) model sequential behavior by moving through states step-by-step on clock edges. At each rising clock edge, the FSM checks its current state and inputs, then decides the next state and output. If inputs don't trigger a change, the FSM stays in the same state. This synchronous update ensures predictable and stable behavior. The example code shows a simple FSM switching between IDLE and RUN states based on start and stop inputs. The execution table traces each clock cycle, showing state and output changes. This stepwise process is why FSMs are used to model sequential logic in hardware design.