Why FSMs model sequential behavior in Verilog - See It in Action

Why FSMs Model Sequential Behavior

📖 Scenario: Imagine you want to control a simple traffic light system that changes lights in a fixed order: green, yellow, then red, and repeats. This system needs to remember its current light and change to the next one in sequence every time a timer finishes. This is a perfect example of sequential behavior, where the next action depends on the current state.

🎯 Goal: You will build a simple Finite State Machine (FSM) in Verilog that models this traffic light sequence. This will show how FSMs help us model systems that change step-by-step over time.

📋 What You'll Learn

Create a Verilog module with states representing traffic light colors

Use a register to hold the current state

Use a clock input to move from one state to the next

Output the current light color as signals

Print the current state in simulation to observe the sequence

💡 Why This Matters

🌍 Real World

Traffic lights, vending machines, and many control systems use FSMs to remember their current step and decide what to do next.

💼 Career

Understanding FSMs is essential for hardware design, embedded systems, and digital logic jobs where controlling sequences and states is common.

1

Define the traffic light states

Create a Verilog module called traffic_light with an input clk and output registers green, yellow, and red. Inside the module, define a typedef enum logic [1:0] called state_t with states GREEN = 2'b00, YELLOW = 2'b01, and RED = 2'b10. Declare a state_t register called current_state.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
// Your code here

Hint

Use typedef enum logic [1:0] to define states and declare current_state as that type.

2

Initialize the current state

Inside the traffic_light module, add an initial block that sets current_state to GREEN at the start.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    // Your code here

Hint

Use an initial block to set the starting state.

3

Create the state transition logic

Add an always_ff @(posedge clk) block inside the module that updates current_state to the next state in sequence: from GREEN to YELLOW, from YELLOW to RED, and from RED back to GREEN.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    initial begin
        current_state = GREEN;
    end
    // Your code here

Hint

Use a case statement inside always_ff @(posedge clk) to update current_state.

4

Output the current light and display state

Assign the outputs green, yellow, and red to be high only when current_state matches their color. Add an initial block with a forever loop that waits for the clock and uses $display to print the current state name as a string.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    initial begin
        current_state = GREEN;
    end
    always_ff @(posedge clk) begin
        case (current_state)
            GREEN: current_state <= YELLOW;
            YELLOW: current_state <= RED;
            RED: current_state <= GREEN;
            default: current_state <= GREEN;
        endcase
    end
    // Your code here

Hint

Use continuous assignments for outputs and a forever @(posedge clk) loop with $display to print states.

Practice

1.

Why do FSMs (Finite State Machines) model sequential behavior effectively in Verilog?

easy

A. Because they execute all states simultaneously without memory.

B. Because they only use combinational logic without any clock.

C. Because they move through a series of states one after another, remembering past states.

D. Because they randomly change states without any order.

Solution

1. Step 1: Understand FSM state transitions

   FSMs move step-by-step through states, which models sequences of actions over time.

2. Step 2: Recognize memory role in FSMs

   FSMs remember the current state, so they know what to do next based on past states.

3. Final Answer:

   Because they move through a series of states one after another, remembering past states. -> Option C

4. Quick Check:

   FSMs use states and memory = Because they move through a series of states one after another, remembering past states. [OK]

Hint: FSMs remember past states to model sequences [OK]

Common Mistakes:

• Thinking FSMs run all states at once
• Confusing FSMs with purely combinational logic
• Assuming FSMs change states randomly

2.

Which Verilog code snippet correctly declares a state register for an FSM?

module fsm_example(clk, reset);
  input clk, reset;
  // Which line correctly declares the state register?
  // A) reg [1:0] state;
  // B) wire state;
  // C) integer state;
  // D) reg state = 0;
endmodule

easy

A. reg state = 0;

B. wire state;

C. integer state;

D. reg [1:0] state;

Solution

1. Step 1: Identify correct register declaration for FSM state

   FSM states are stored in registers, typically as a vector for multiple states, so reg [1:0] state; is correct.

2. Step 2: Eliminate incorrect options

   wire cannot store state, integer is not typical for FSM states, and reg state = 0; lacks bit width for multiple states.

3. Final Answer:

   reg [1:0] state; -> Option D

4. Quick Check:

   FSM state needs reg with bit width = reg [1:0] state; [OK]

Hint: FSM states need reg with bit width, not wire [OK]

Common Mistakes:

• Using wire instead of reg for state
• Not specifying bit width for multiple states
• Initializing reg in declaration (not synthesizable)

3.

What is the output of this FSM code snippet after 3 clock cycles if reset is 0 and initial state is 2'b00?

reg [1:0] state;
always @(posedge clk or posedge reset) begin
  if (reset) state <= 2'b00;
  else begin
    case(state)
      2'b00: state <= 2'b01;
      2'b01: state <= 2'b10;
      2'b10: state <= 2'b00;
      default: state <= 2'b00;
    endcase
  end
end
// What is state after 3 clock cycles?

medium

A. 2'b00

B. 2'b01

C. 2'b10

D. 2'b11

Solution

1. Step 1: Trace state transitions from initial state

   Start at 2'b00, cycle 1: state=2'b01, cycle 2: state=2'b10, cycle 3: state=2'b00.

2. Step 2: Confirm state after 3 cycles

   After 3 clock cycles, the FSM returns to 2'b00 as per the cycle defined.

3. Final Answer:

   2'b00 -> Option A

4. Quick Check:

   State cycles 00->01->10->00 = 2'b00 [OK]

Hint: Follow state changes step-by-step per clock [OK]

Common Mistakes:

• Forgetting initial state
• Counting reset as a clock cycle
• Misreading state transitions

4.

Identify the error in this FSM snippet that prevents correct sequential behavior:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state = 2'b01;
    2'b01: state = 2'b10;
    2'b10: state = 2'b00;
  endcase
end

medium

A. All of the above.

B. Missing reset condition to initialize state.

C. No default case in the case statement.

D. Using blocking assignment (=) instead of non-blocking (<=) inside always block.

Solution

1. Step 1: Check assignment type in sequential always block

   Blocking assignment (=) should be replaced with non-blocking (<=) for correct sequential logic.

2. Step 2: Check for reset and default case

   There is no reset to initialize state, and no default case to handle unexpected states.

3. Final Answer:

   All of the above. -> Option A

4. Quick Check:

   Blocking assignment + no reset + no default = All of the above. [OK]

Hint: Use <= in sequential blocks and always include reset [OK]

Common Mistakes:

• Using = instead of <= in always block
• Forgetting reset logic
• Ignoring default case in FSM

5.

You want to design an FSM in Verilog that controls a traffic light sequence: Green (G), Yellow (Y), Red (R), then back to Green. Which approach best models this sequential behavior?

hard

A. Use random state changes without memory to simulate traffic flow.

B. Use a state register with states G, Y, R and transition on clock edges remembering past state.

C. Use combinational logic only to set lights based on input switches.

D. Use multiple always blocks without a state register.

Solution

1. Step 1: Identify FSM role in traffic light control

   Traffic lights follow a fixed sequence, so an FSM with states for each light is ideal.

2. Step 2: Understand why state register and clock are needed

   The FSM uses a state register to remember current light and transitions on clock edges to next state.

3. Final Answer:

   Use a state register with states G, Y, R and transition on clock edges remembering past state. -> Option B

4. Quick Check:

   Sequential control with state memory = Use a state register with states G, Y, R and transition on clock edges remembering past state. [OK]

Hint: Model sequences with states and clocked transitions [OK]

Common Mistakes:

• Trying to use combinational logic only
• Ignoring state memory for sequence
• Using random or multiple always blocks without state