Why FSMs model sequential behavior in Verilog - See It in Action

Why FSMs Model Sequential Behavior

📖 Scenario: Imagine you want to control a simple traffic light system that changes lights in a fixed order: green, yellow, then red, and repeats. This system needs to remember its current light and change to the next one in sequence every time a timer finishes. This is a perfect example of sequential behavior, where the next action depends on the current state.

🎯 Goal: You will build a simple Finite State Machine (FSM) in Verilog that models this traffic light sequence. This will show how FSMs help us model systems that change step-by-step over time.

📋 What You'll Learn

Create a Verilog module with states representing traffic light colors

Use a register to hold the current state

Use a clock input to move from one state to the next

Output the current light color as signals

Print the current state in simulation to observe the sequence

💡 Why This Matters

🌍 Real World

Traffic lights, vending machines, and many control systems use FSMs to remember their current step and decide what to do next.

💼 Career

Understanding FSMs is essential for hardware design, embedded systems, and digital logic jobs where controlling sequences and states is common.

1

Define the traffic light states

Create a Verilog module called traffic_light with an input clk and output registers green, yellow, and red. Inside the module, define a typedef enum logic [1:0] called state_t with states GREEN = 2'b00, YELLOW = 2'b01, and RED = 2'b10. Declare a state_t register called current_state.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
// Your code here

Need a hint?

Use typedef enum logic [1:0] to define states and declare current_state as that type.

2

Initialize the current state

Inside the traffic_light module, add an initial block that sets current_state to GREEN at the start.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    // Your code here

Need a hint?

Use an initial block to set the starting state.

3

Create the state transition logic

Add an always_ff @(posedge clk) block inside the module that updates current_state to the next state in sequence: from GREEN to YELLOW, from YELLOW to RED, and from RED back to GREEN.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    initial begin
        current_state = GREEN;
    end
    // Your code here

Need a hint?

Use a case statement inside always_ff @(posedge clk) to update current_state.

4

Output the current light and display state

Assign the outputs green, yellow, and red to be high only when current_state matches their color. Add an initial block with a forever loop that waits for the clock and uses $display to print the current state name as a string.

Verilog

module traffic_light(input logic clk, output logic green, yellow, red);
    typedef enum logic [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10} state_t;
    state_t current_state;
    initial begin
        current_state = GREEN;
    end
    always_ff @(posedge clk) begin
        case (current_state)
            GREEN: current_state <= YELLOW;
            YELLOW: current_state <= RED;
            RED: current_state <= GREEN;
            default: current_state <= GREEN;
        endcase
    end
    // Your code here

Need a hint?

Use continuous assignments for outputs and a forever @(posedge clk) loop with $display to print states.