Why FSMs model sequential behavior in Verilog - Performance Analysis

Time Complexity: Why FSMs model sequential behavior

O(n)

Understanding Time Complexity

We want to understand how the time it takes for a finite state machine (FSM) to run changes as it processes inputs.

How does the FSM's work grow when it moves through states step by step?

Scenario Under Consideration

Analyze the time complexity of the following FSM code snippet.

module simple_fsm(
  input clk,
  input reset,
  input in,
  output reg out_state
);
  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S2 : S0;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always_ff @(posedge clk) begin
    out_state <= (state == S2);
  end
endmodule
    

This FSM moves through states S0, S1, and S2 based on input, updating state on each clock cycle.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The FSM updates its state once every clock cycle.
• How many times: It repeats this update for each clock tick, sequentially moving through states.

How Execution Grows With Input

The FSM processes one input per clock cycle, moving step by step through states.

Input Size (n)	Approx. Operations
10	10 state updates
100	100 state updates
1000	1000 state updates

Pattern observation: The number of operations grows directly with the number of inputs processed.

Final Time Complexity

Time Complexity: O(n)

This means the FSM takes time proportional to the number of inputs it processes, updating states one by one.

Common Mistake

[X] Wrong: "FSMs process all inputs at once, so time does not grow with input size."

[OK] Correct: FSMs update state sequentially on each clock cycle, so processing more inputs means more steps and more time.

Interview Connect

Understanding how FSMs handle inputs step by step helps you explain how hardware designs manage sequences, a key skill in digital design discussions.

Self-Check

"What if the FSM could update multiple states in one clock cycle? How would the time complexity change?"

Practice

1.

Why do FSMs (Finite State Machines) model sequential behavior effectively in Verilog?

easy

A. Because they execute all states simultaneously without memory.

B. Because they only use combinational logic without any clock.

C. Because they move through a series of states one after another, remembering past states.

D. Because they randomly change states without any order.

Solution

1. Step 1: Understand FSM state transitions

   FSMs move step-by-step through states, which models sequences of actions over time.

2. Step 2: Recognize memory role in FSMs

   FSMs remember the current state, so they know what to do next based on past states.

3. Final Answer:

   Because they move through a series of states one after another, remembering past states. -> Option C

4. Quick Check:

   FSMs use states and memory = Because they move through a series of states one after another, remembering past states. [OK]

Hint: FSMs remember past states to model sequences [OK]

Common Mistakes:

• Thinking FSMs run all states at once
• Confusing FSMs with purely combinational logic
• Assuming FSMs change states randomly

2.

Which Verilog code snippet correctly declares a state register for an FSM?

module fsm_example(clk, reset);
  input clk, reset;
  // Which line correctly declares the state register?
  // A) reg [1:0] state;
  // B) wire state;
  // C) integer state;
  // D) reg state = 0;
endmodule

easy

A. reg state = 0;

B. wire state;

C. integer state;

D. reg [1:0] state;

Solution

1. Step 1: Identify correct register declaration for FSM state

   FSM states are stored in registers, typically as a vector for multiple states, so reg [1:0] state; is correct.

2. Step 2: Eliminate incorrect options

   wire cannot store state, integer is not typical for FSM states, and reg state = 0; lacks bit width for multiple states.

3. Final Answer:

   reg [1:0] state; -> Option D

4. Quick Check:

   FSM state needs reg with bit width = reg [1:0] state; [OK]

Hint: FSM states need reg with bit width, not wire [OK]

Common Mistakes:

• Using wire instead of reg for state
• Not specifying bit width for multiple states
• Initializing reg in declaration (not synthesizable)

3.

What is the output of this FSM code snippet after 3 clock cycles if reset is 0 and initial state is 2'b00?

reg [1:0] state;
always @(posedge clk or posedge reset) begin
  if (reset) state <= 2'b00;
  else begin
    case(state)
      2'b00: state <= 2'b01;
      2'b01: state <= 2'b10;
      2'b10: state <= 2'b00;
      default: state <= 2'b00;
    endcase
  end
end
// What is state after 3 clock cycles?

medium

A. 2'b00

B. 2'b01

C. 2'b10

D. 2'b11

Solution

1. Step 1: Trace state transitions from initial state

   Start at 2'b00, cycle 1: state=2'b01, cycle 2: state=2'b10, cycle 3: state=2'b00.

2. Step 2: Confirm state after 3 cycles

   After 3 clock cycles, the FSM returns to 2'b00 as per the cycle defined.

3. Final Answer:

   2'b00 -> Option A

4. Quick Check:

   State cycles 00->01->10->00 = 2'b00 [OK]

Hint: Follow state changes step-by-step per clock [OK]

Common Mistakes:

• Forgetting initial state
• Counting reset as a clock cycle
• Misreading state transitions

4.

Identify the error in this FSM snippet that prevents correct sequential behavior:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state = 2'b01;
    2'b01: state = 2'b10;
    2'b10: state = 2'b00;
  endcase
end

medium

A. All of the above.

B. Missing reset condition to initialize state.

C. No default case in the case statement.

D. Using blocking assignment (=) instead of non-blocking (<=) inside always block.

Solution

1. Step 1: Check assignment type in sequential always block

   Blocking assignment (=) should be replaced with non-blocking (<=) for correct sequential logic.

2. Step 2: Check for reset and default case

   There is no reset to initialize state, and no default case to handle unexpected states.

3. Final Answer:

   All of the above. -> Option A

4. Quick Check:

   Blocking assignment + no reset + no default = All of the above. [OK]

Hint: Use <= in sequential blocks and always include reset [OK]

Common Mistakes:

• Using = instead of <= in always block
• Forgetting reset logic
• Ignoring default case in FSM

5.

You want to design an FSM in Verilog that controls a traffic light sequence: Green (G), Yellow (Y), Red (R), then back to Green. Which approach best models this sequential behavior?

hard

A. Use random state changes without memory to simulate traffic flow.

B. Use a state register with states G, Y, R and transition on clock edges remembering past state.

C. Use combinational logic only to set lights based on input switches.

D. Use multiple always blocks without a state register.

Solution

1. Step 1: Identify FSM role in traffic light control

   Traffic lights follow a fixed sequence, so an FSM with states for each light is ideal.

2. Step 2: Understand why state register and clock are needed

   The FSM uses a state register to remember current light and transitions on clock edges to next state.

3. Final Answer:

   Use a state register with states G, Y, R and transition on clock edges remembering past state. -> Option B

4. Quick Check:

   Sequential control with state memory = Use a state register with states G, Y, R and transition on clock edges remembering past state. [OK]

Hint: Model sequences with states and clocked transitions [OK]

Common Mistakes:

• Trying to use combinational logic only
• Ignoring state memory for sequence
• Using random or multiple always blocks without state