Why FSMs model sequential behavior in Verilog - Performance Analysis

Time Complexity: Why FSMs model sequential behavior

O(n)

Understanding Time Complexity

We want to understand how the time it takes for a finite state machine (FSM) to run changes as it processes inputs.

How does the FSM's work grow when it moves through states step by step?

Scenario Under Consideration

Analyze the time complexity of the following FSM code snippet.

module simple_fsm(
  input clk,
  input reset,
  input in,
  output reg out_state
);
  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S2 : S0;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always_ff @(posedge clk) begin
    out_state <= (state == S2);
  end
endmodule
    

This FSM moves through states S0, S1, and S2 based on input, updating state on each clock cycle.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The FSM updates its state once every clock cycle.
• How many times: It repeats this update for each clock tick, sequentially moving through states.

How Execution Grows With Input

The FSM processes one input per clock cycle, moving step by step through states.

Input Size (n)	Approx. Operations
10	10 state updates
100	100 state updates
1000	1000 state updates

Pattern observation: The number of operations grows directly with the number of inputs processed.

Final Time Complexity

Time Complexity: O(n)

This means the FSM takes time proportional to the number of inputs it processes, updating states one by one.

Common Mistake

[X] Wrong: "FSMs process all inputs at once, so time does not grow with input size."

[OK] Correct: FSMs update state sequentially on each clock cycle, so processing more inputs means more steps and more time.

Interview Connect

Understanding how FSMs handle inputs step by step helps you explain how hardware designs manage sequences, a key skill in digital design discussions.

Self-Check

"What if the FSM could update multiple states in one clock cycle? How would the time complexity change?"