Why FSMs model sequential behavior in Verilog - Challenge Your Understanding

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog FSM simulation?

Consider this simple FSM code snippet in Verilog. What will be the value of state after 3 clock cycles?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else begin
      case(state)
        S0: state <= S1;
        S1: state <= S2;
        S2: state <= S0;
        default: state <= S0;
      endcase
    end
  end
endmodule

A 2'b11

B 2'b10

C 2'b01

D 2'b00

💡 Hint

Trace the state changes on each clock rising edge starting from reset.

The FSM starts at S0 (00) after reset. On first clock, it moves to S1 (01), second clock to S2 (10), third clock back to S0 (00). After 3 clocks, the state is S0 (00).

🧠 Conceptual

intermediate

Why do FSMs require clock signals to model sequential behavior?

Which option best explains why FSMs use clock signals to model sequential behavior?

A Clock signals provide power to the FSM circuit to operate continuously.

B Clock signals synchronize state changes to happen at discrete times, ensuring predictable sequence progression.

C Clock signals store the current state value in memory elements permanently.

D Clock signals allow the FSM to execute multiple states simultaneously.

💡 Hint

Think about how FSMs move from one state to another in a controlled manner.

FSMs use clock signals to update their state only at specific times (clock edges). This synchronization ensures the FSM progresses through states in a predictable, step-by-step sequence.

🔧 Debug

advanced

Identify the error causing incorrect FSM state transitions

Given this FSM Verilog code, what is the main reason the FSM does not transition states correctly?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else begin
      case(state)
        S0: state <= S1;
        S1: state <= S2;
        S2: state <= S0;
      endcase
    end
  end
endmodule

A Using blocking assignments (=) inside the always block causes incorrect state updates.

B Missing default case in the case statement causes the FSM to hang.

C Reset signal should be checked on negedge instead of posedge.

D State variables should be declared as wire, not reg.

💡 Hint

Consider the difference between blocking and non-blocking assignments in sequential logic.

In sequential logic (inside always @(posedge clk)), non-blocking assignments (<=) must be used to ensure proper state updates. Using blocking assignments (=) can cause race conditions and incorrect behavior.

📝 Syntax

advanced

Which Verilog code snippet correctly models a Moore FSM?

Choose the code snippet that correctly implements a Moore FSM with states S0 and S1, where output is based only on the current state.

A

always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
  output <= (state == S1);
end

B

always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
end
assign output = (state == S1);

C

always @(state) begin
  case(state)
    S0: output = 0;
    S1: output = 1;
  endcase
end
always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
end

D

always @(posedge clk) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
  output = (state == S1);
end

💡 Hint

Remember Moore FSM outputs depend only on state, not inputs or transitions.

Option C separates output logic (combinational, based on state) from state update logic (sequential, on clock). This matches Moore FSM design principles.

🚀 Application

expert

How does an FSM model sequential behavior in hardware?

Which option best describes how FSMs model sequential behavior in digital circuits?

A FSMs use memory elements like flip-flops to store the current state and combinational logic to determine the next state, updating on clock edges.

B FSMs rely solely on combinational logic gates to produce outputs based on inputs without storing any state.

C FSMs use asynchronous signals to change states immediately when inputs change, without clock synchronization.

D FSMs use analog components to continuously vary outputs based on input voltage levels.

💡 Hint

Think about how digital circuits remember past events to behave sequentially.

FSMs combine memory elements (flip-flops) that hold the current state and combinational logic that computes the next state. The clock signal triggers state updates, enabling sequential behavior.

Practice

1.

Why do FSMs (Finite State Machines) model sequential behavior effectively in Verilog?

easy

A. Because they execute all states simultaneously without memory.

B. Because they only use combinational logic without any clock.

C. Because they move through a series of states one after another, remembering past states.

D. Because they randomly change states without any order.

Solution

1. Step 1: Understand FSM state transitions

   FSMs move step-by-step through states, which models sequences of actions over time.

2. Step 2: Recognize memory role in FSMs

   FSMs remember the current state, so they know what to do next based on past states.

3. Final Answer:

   Because they move through a series of states one after another, remembering past states. -> Option C

4. Quick Check:

   FSMs use states and memory = Because they move through a series of states one after another, remembering past states. [OK]

Hint: FSMs remember past states to model sequences [OK]

Common Mistakes:

• Thinking FSMs run all states at once
• Confusing FSMs with purely combinational logic
• Assuming FSMs change states randomly

2.

Which Verilog code snippet correctly declares a state register for an FSM?

module fsm_example(clk, reset);
  input clk, reset;
  // Which line correctly declares the state register?
  // A) reg [1:0] state;
  // B) wire state;
  // C) integer state;
  // D) reg state = 0;
endmodule

easy

A. reg state = 0;

B. wire state;

C. integer state;

D. reg [1:0] state;

Solution

1. Step 1: Identify correct register declaration for FSM state

   FSM states are stored in registers, typically as a vector for multiple states, so reg [1:0] state; is correct.

2. Step 2: Eliminate incorrect options

   wire cannot store state, integer is not typical for FSM states, and reg state = 0; lacks bit width for multiple states.

3. Final Answer:

   reg [1:0] state; -> Option D

4. Quick Check:

   FSM state needs reg with bit width = reg [1:0] state; [OK]

Hint: FSM states need reg with bit width, not wire [OK]

Common Mistakes:

• Using wire instead of reg for state
• Not specifying bit width for multiple states
• Initializing reg in declaration (not synthesizable)

3.

What is the output of this FSM code snippet after 3 clock cycles if reset is 0 and initial state is 2'b00?

reg [1:0] state;
always @(posedge clk or posedge reset) begin
  if (reset) state <= 2'b00;
  else begin
    case(state)
      2'b00: state <= 2'b01;
      2'b01: state <= 2'b10;
      2'b10: state <= 2'b00;
      default: state <= 2'b00;
    endcase
  end
end
// What is state after 3 clock cycles?

medium

A. 2'b00

B. 2'b01

C. 2'b10

D. 2'b11

Solution

1. Step 1: Trace state transitions from initial state

   Start at 2'b00, cycle 1: state=2'b01, cycle 2: state=2'b10, cycle 3: state=2'b00.

2. Step 2: Confirm state after 3 cycles

   After 3 clock cycles, the FSM returns to 2'b00 as per the cycle defined.

3. Final Answer:

   2'b00 -> Option A

4. Quick Check:

   State cycles 00->01->10->00 = 2'b00 [OK]

Hint: Follow state changes step-by-step per clock [OK]

Common Mistakes:

• Forgetting initial state
• Counting reset as a clock cycle
• Misreading state transitions

4.

Identify the error in this FSM snippet that prevents correct sequential behavior:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state = 2'b01;
    2'b01: state = 2'b10;
    2'b10: state = 2'b00;
  endcase
end

medium

A. All of the above.

B. Missing reset condition to initialize state.

C. No default case in the case statement.

D. Using blocking assignment (=) instead of non-blocking (<=) inside always block.

Solution

1. Step 1: Check assignment type in sequential always block

   Blocking assignment (=) should be replaced with non-blocking (<=) for correct sequential logic.

2. Step 2: Check for reset and default case

   There is no reset to initialize state, and no default case to handle unexpected states.

3. Final Answer:

   All of the above. -> Option A

4. Quick Check:

   Blocking assignment + no reset + no default = All of the above. [OK]

Hint: Use <= in sequential blocks and always include reset [OK]

Common Mistakes:

• Using = instead of <= in always block
• Forgetting reset logic
• Ignoring default case in FSM

5.

You want to design an FSM in Verilog that controls a traffic light sequence: Green (G), Yellow (Y), Red (R), then back to Green. Which approach best models this sequential behavior?

hard

A. Use random state changes without memory to simulate traffic flow.

B. Use a state register with states G, Y, R and transition on clock edges remembering past state.

C. Use combinational logic only to set lights based on input switches.

D. Use multiple always blocks without a state register.

Solution

1. Step 1: Identify FSM role in traffic light control

   Traffic lights follow a fixed sequence, so an FSM with states for each light is ideal.

2. Step 2: Understand why state register and clock are needed

   The FSM uses a state register to remember current light and transitions on clock edges to next state.

3. Final Answer:

   Use a state register with states G, Y, R and transition on clock edges remembering past state. -> Option B

4. Quick Check:

   Sequential control with state memory = Use a state register with states G, Y, R and transition on clock edges remembering past state. [OK]

Hint: Model sequences with states and clocked transitions [OK]

Common Mistakes:

• Trying to use combinational logic only
• Ignoring state memory for sequence
• Using random or multiple always blocks without state