Why FSMs model sequential behavior in Verilog - Challenge Your Understanding

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog FSM simulation?

Consider this simple FSM code snippet in Verilog. What will be the value of state after 3 clock cycles?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else begin
      case(state)
        S0: state <= S1;
        S1: state <= S2;
        S2: state <= S0;
        default: state <= S0;
      endcase
    end
  end
endmodule

A 2'b11

B 2'b10

C 2'b01

D 2'b00

💡 Hint

Trace the state changes on each clock rising edge starting from reset.

The FSM starts at S0 (00) after reset. On first clock, it moves to S1 (01), second clock to S2 (10), third clock back to S0 (00). After 3 clocks, the state is S0 (00).

🧠 Conceptual

intermediate

Why do FSMs require clock signals to model sequential behavior?

Which option best explains why FSMs use clock signals to model sequential behavior?

A Clock signals provide power to the FSM circuit to operate continuously.

B Clock signals synchronize state changes to happen at discrete times, ensuring predictable sequence progression.

C Clock signals store the current state value in memory elements permanently.

D Clock signals allow the FSM to execute multiple states simultaneously.

💡 Hint

Think about how FSMs move from one state to another in a controlled manner.

FSMs use clock signals to update their state only at specific times (clock edges). This synchronization ensures the FSM progresses through states in a predictable, step-by-step sequence.

🔧 Debug

advanced

Identify the error causing incorrect FSM state transitions

Given this FSM Verilog code, what is the main reason the FSM does not transition states correctly?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else begin
      case(state)
        S0: state <= S1;
        S1: state <= S2;
        S2: state <= S0;
      endcase
    end
  end
endmodule

A Using blocking assignments (=) inside the always block causes incorrect state updates.

B Missing default case in the case statement causes the FSM to hang.

C Reset signal should be checked on negedge instead of posedge.

D State variables should be declared as wire, not reg.

💡 Hint

Consider the difference between blocking and non-blocking assignments in sequential logic.

In sequential logic (inside always @(posedge clk)), non-blocking assignments (<=) must be used to ensure proper state updates. Using blocking assignments (=) can cause race conditions and incorrect behavior.

📝 Syntax

advanced

Which Verilog code snippet correctly models a Moore FSM?

Choose the code snippet that correctly implements a Moore FSM with states S0 and S1, where output is based only on the current state.

A

always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
  output <= (state == S1);
end

B

always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
end
assign output = (state == S1);

C

always @(state) begin
  case(state)
    S0: output = 0;
    S1: output = 1;
  endcase
end
always @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
end

D

always @(posedge clk) begin
  if (reset) state <= S0;
  else case(state)
    S0: state <= S1;
    S1: state <= S0;
  endcase
  output = (state == S1);
end

💡 Hint

Remember Moore FSM outputs depend only on state, not inputs or transitions.

Option C separates output logic (combinational, based on state) from state update logic (sequential, on clock). This matches Moore FSM design principles.

🚀 Application

expert

How does an FSM model sequential behavior in hardware?

Which option best describes how FSMs model sequential behavior in digital circuits?

A FSMs use memory elements like flip-flops to store the current state and combinational logic to determine the next state, updating on clock edges.

B FSMs rely solely on combinational logic gates to produce outputs based on inputs without storing any state.

C FSMs use asynchronous signals to change states immediately when inputs change, without clock synchronization.

D FSMs use analog components to continuously vary outputs based on input voltage levels.

💡 Hint

Think about how digital circuits remember past events to behave sequentially.

FSMs combine memory elements (flip-flops) that hold the current state and combinational logic that computes the next state. The clock signal triggers state updates, enabling sequential behavior.