Why FSMs model sequential behavior in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a clock-sensitive block in Verilog.

Verilog

always @(posedge [1]) begin
    // sequential logic here
end

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Aclk

Breset

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using data or reset signals instead of the clock in the sensitivity list.

The posedge clk sensitivity list triggers the block on the rising edge of the clock, which is essential for sequential behavior.

2fill in blank

medium

Complete the code to define a state register that updates on the clock edge.

Verilog

reg [1:0] state;
always @(posedge clk) begin
    state <= [1];
end

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Anext_state

Bstate

Cinput_signal

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning state to itself, which causes no state change.

The state register updates to next_state on the clock's rising edge, modeling sequential state transitions.

3fill in blank

hard

Fix the error in the state transition logic by completing the conditional statement.

Verilog

always @(posedge clk) begin
    if (reset) begin
        state <= 2'b00;
    end else if (input_signal [1] 1'b1) begin
        state <= 2'b01;
    end
end

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A!=

B==

C=

D<=

Attempts:

3 left

💡 Hint

Common Mistakes

Using = instead of == in the if condition.

The equality operator == is needed to compare input_signal to 1'b1. Using = causes an assignment error.

4fill in blank

hard

Fill both blanks to complete the combinational logic for next state assignment.

Verilog

always @(*) begin
    case (state)
        2'b00: next_state = (input_signal [1] 1'b1) ? 2'b01 : 2'b00;
        2'b01: next_state = (input_signal [2] 1'b0) ? 2'b00 : 2'b01;
        default: next_state = 2'b00;
    endcase
end

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A==

B!=

C<=

D>=

Attempts:

3 left

💡 Hint

Common Mistakes

Using assignment operators instead of comparison operators in conditions.

The next state depends on whether input_signal equals or does not equal 1'b1 or 1'b0. Using == and != correctly models this logic.

5fill in blank

hard

Fill all three blanks to complete the FSM module with state, next_state, and clock sensitivity.

Verilog

module fsm(input clk, input reset, input input_signal, output reg [1:0] state);
    reg [1:0] [1];

    always @([2]) begin
        if (reset) begin
            state <= 2'b00;
        end else begin
            state <= [3];
        end
    end
endmodule

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Anext_state

Bposedge clk

Dnegedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong sensitivity list like reset edge instead of clock edge.

Confusing state and next_state registers.

The next_state register holds the upcoming state. The always block triggers on the clock's rising edge (posedge clk). The state register updates to next_state on each clock cycle.