Why FSMs model sequential behavior in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a clock-sensitive block in Verilog.

Verilog

always @(posedge [1]) begin
    // sequential logic here
end

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using data or reset signals instead of the clock in the sensitivity list.

The posedge clk sensitivity list triggers the block on the rising edge of the clock, which is essential for sequential behavior.

2fill in blank

medium

Complete the code to define a state register that updates on the clock edge.

Verilog

reg [1:0] state;
always @(posedge clk) begin
    state <= [1];
end

Drag options to blanks, or click blank then click option'

Anext_state

Bstate

Cinput_signal

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning state to itself, which causes no state change.

The state register updates to next_state on the clock's rising edge, modeling sequential state transitions.

3fill in blank

hard

Fix the error in the state transition logic by completing the conditional statement.

Verilog

always @(posedge clk) begin
    if (reset) begin
        state <= 2'b00;
    end else if (input_signal [1] 1'b1) begin
        state <= 2'b01;
    end
end

Drag options to blanks, or click blank then click option'

A!=

B==

C=

D<=

Attempts:

3 left

💡 Hint

Common Mistakes

Using = instead of == in the if condition.

The equality operator == is needed to compare input_signal to 1'b1. Using = causes an assignment error.

4fill in blank

hard

Fill both blanks to complete the combinational logic for next state assignment.

Verilog

always @(*) begin
    case (state)
        2'b00: next_state = (input_signal [1] 1'b1) ? 2'b01 : 2'b00;
        2'b01: next_state = (input_signal [2] 1'b0) ? 2'b00 : 2'b01;
        default: next_state = 2'b00;
    endcase
end

Drag options to blanks, or click blank then click option'

A==

B!=

C<=

D>=

Attempts:

3 left

💡 Hint

Common Mistakes

Using assignment operators instead of comparison operators in conditions.

The next state depends on whether input_signal equals or does not equal 1'b1 or 1'b0. Using == and != correctly models this logic.

5fill in blank

hard

Fill all three blanks to complete the FSM module with state, next_state, and clock sensitivity.

Verilog

module fsm(input clk, input reset, input input_signal, output reg [1:0] state);
    reg [1:0] [1];

    always @([2]) begin
        if (reset) begin
            state <= 2'b00;
        end else begin
            state <= [3];
        end
    end
endmodule

Drag options to blanks, or click blank then click option'

Anext_state

Bposedge clk

Dnegedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong sensitivity list like reset edge instead of clock edge.

Confusing state and next_state registers.

The next_state register holds the upcoming state. The always block triggers on the clock's rising edge (posedge clk). The state register updates to next_state on each clock cycle.

Practice

1.

Why do FSMs (Finite State Machines) model sequential behavior effectively in Verilog?

easy

A. Because they execute all states simultaneously without memory.

B. Because they only use combinational logic without any clock.

C. Because they move through a series of states one after another, remembering past states.

D. Because they randomly change states without any order.

Solution

1. Step 1: Understand FSM state transitions

   FSMs move step-by-step through states, which models sequences of actions over time.

2. Step 2: Recognize memory role in FSMs

   FSMs remember the current state, so they know what to do next based on past states.

3. Final Answer:

   Because they move through a series of states one after another, remembering past states. -> Option C

4. Quick Check:

   FSMs use states and memory = Because they move through a series of states one after another, remembering past states. [OK]

Hint: FSMs remember past states to model sequences [OK]

Common Mistakes:

• Thinking FSMs run all states at once
• Confusing FSMs with purely combinational logic
• Assuming FSMs change states randomly

2.

Which Verilog code snippet correctly declares a state register for an FSM?

module fsm_example(clk, reset);
  input clk, reset;
  // Which line correctly declares the state register?
  // A) reg [1:0] state;
  // B) wire state;
  // C) integer state;
  // D) reg state = 0;
endmodule

easy

A. reg state = 0;

B. wire state;

C. integer state;

D. reg [1:0] state;

Solution

1. Step 1: Identify correct register declaration for FSM state

   FSM states are stored in registers, typically as a vector for multiple states, so reg [1:0] state; is correct.

2. Step 2: Eliminate incorrect options

   wire cannot store state, integer is not typical for FSM states, and reg state = 0; lacks bit width for multiple states.

3. Final Answer:

   reg [1:0] state; -> Option D

4. Quick Check:

   FSM state needs reg with bit width = reg [1:0] state; [OK]

Hint: FSM states need reg with bit width, not wire [OK]

Common Mistakes:

• Using wire instead of reg for state
• Not specifying bit width for multiple states
• Initializing reg in declaration (not synthesizable)

3.

What is the output of this FSM code snippet after 3 clock cycles if reset is 0 and initial state is 2'b00?

reg [1:0] state;
always @(posedge clk or posedge reset) begin
  if (reset) state <= 2'b00;
  else begin
    case(state)
      2'b00: state <= 2'b01;
      2'b01: state <= 2'b10;
      2'b10: state <= 2'b00;
      default: state <= 2'b00;
    endcase
  end
end
// What is state after 3 clock cycles?

medium

A. 2'b00

B. 2'b01

C. 2'b10

D. 2'b11

Solution

1. Step 1: Trace state transitions from initial state

   Start at 2'b00, cycle 1: state=2'b01, cycle 2: state=2'b10, cycle 3: state=2'b00.

2. Step 2: Confirm state after 3 cycles

   After 3 clock cycles, the FSM returns to 2'b00 as per the cycle defined.

3. Final Answer:

   2'b00 -> Option A

4. Quick Check:

   State cycles 00->01->10->00 = 2'b00 [OK]

Hint: Follow state changes step-by-step per clock [OK]

Common Mistakes:

• Forgetting initial state
• Counting reset as a clock cycle
• Misreading state transitions

4.

Identify the error in this FSM snippet that prevents correct sequential behavior:

reg [1:0] state;
always @(posedge clk) begin
  case(state)
    2'b00: state = 2'b01;
    2'b01: state = 2'b10;
    2'b10: state = 2'b00;
  endcase
end

medium

A. All of the above.

B. Missing reset condition to initialize state.

C. No default case in the case statement.

D. Using blocking assignment (=) instead of non-blocking (<=) inside always block.

Solution

1. Step 1: Check assignment type in sequential always block

   Blocking assignment (=) should be replaced with non-blocking (<=) for correct sequential logic.

2. Step 2: Check for reset and default case

   There is no reset to initialize state, and no default case to handle unexpected states.

3. Final Answer:

   All of the above. -> Option A

4. Quick Check:

   Blocking assignment + no reset + no default = All of the above. [OK]

Hint: Use <= in sequential blocks and always include reset [OK]

Common Mistakes:

• Using = instead of <= in always block
• Forgetting reset logic
• Ignoring default case in FSM

5.

You want to design an FSM in Verilog that controls a traffic light sequence: Green (G), Yellow (Y), Red (R), then back to Green. Which approach best models this sequential behavior?

hard

A. Use random state changes without memory to simulate traffic flow.

B. Use a state register with states G, Y, R and transition on clock edges remembering past state.

C. Use combinational logic only to set lights based on input switches.

D. Use multiple always blocks without a state register.

Solution

1. Step 1: Identify FSM role in traffic light control

   Traffic lights follow a fixed sequence, so an FSM with states for each light is ideal.

2. Step 2: Understand why state register and clock are needed

   The FSM uses a state register to remember current light and transitions on clock edges to next state.

3. Final Answer:

   Use a state register with states G, Y, R and transition on clock edges remembering past state. -> Option B

4. Quick Check:

   Sequential control with state memory = Use a state register with states G, Y, R and transition on clock edges remembering past state. [OK]

Hint: Model sequences with states and clocked transitions [OK]

Common Mistakes:

• Trying to use combinational logic only
• Ignoring state memory for sequence
• Using random or multiple always blocks without state