When to use blocking (combinational) in Verilog - Step-by-Step Execution

Concept Flow - When to use blocking (combinational)

Start Combinational Logic

↓

Use Blocking Assignments (=)

↓

Evaluate statements in order

↓

Update variables immediately

↓

Output combinational signals

↓

End Combinational Logic

Blocking assignments (=) are used in combinational logic to evaluate statements in order and update variables immediately, reflecting real combinational behavior.

Execution Sample

Verilog

always @(*) begin
  a = b + c;
  d = a + 1;
end

This code uses blocking assignments to compute 'a' then 'd' in order, modeling combinational logic.

Execution Table

Step	Statement	Variable Before	Evaluation	Variable After
1	a = b + c;	b=2, c=3, a=0	a = 2 + 3	a=5
2	d = a + 1;	a=5, d=0	d = 5 + 1	d=6
3	End always block	a=5, d=6	No change	a=5, d=6

💡 All statements executed in order with blocking assignments, variables updated immediately.

Variable Tracker

Variable	Start	After Step 1	After Step 2	Final
a	0	5	5	5
d	0	0	6	6
b	2	2	2	2
c	3	3	3	3

Key Moments - 2 Insights

Why do we use blocking assignments (=) in combinational logic?

Because blocking assignments update variables immediately in order, matching how combinational logic works, as shown in execution_table steps 1 and 2.

What happens if we use non-blocking assignments (<=) in combinational logic?

Non-blocking assignments delay updates until the end of the time step, which can cause incorrect intermediate values in combinational logic, unlike the immediate updates seen in the execution_table.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'a' after step 1?

A 0

B 5

C 6

D 2

💡 Hint

Refer to the 'Variable After' column in row for step 1.

At which step does 'd' get its final value?

A Step 2

B Step 1

C Step 3

D Never

💡 Hint

Check the 'Variable After' column for 'd' in each step.

If we replaced '=' with '<=' in the code, how would the variable updates change?

A Variables update immediately in order

B Variables update randomly

C Variables update only at the end of the block

D Variables do not update

💡 Hint

See key_moments explanation about non-blocking assignments delaying updates.

Concept Snapshot

Use blocking assignments (=) in combinational always blocks.
Statements execute in order, variables update immediately.
This models real combinational logic behavior.
Avoid non-blocking (<=) in combinational logic to prevent incorrect delays.
Example:
always @(*) begin a = b + c; d = a + 1; end

Full Transcript

In Verilog, blocking assignments (=) are used in combinational logic blocks to ensure statements execute in order and variables update immediately. This matches how combinational circuits work in hardware. For example, in the code 'always @(*) begin a = b + c; d = a + 1; end', 'a' is updated first, then 'd' uses the new value of 'a'. The execution table shows step-by-step how variables change. Using non-blocking assignments (<=) here would delay updates and cause incorrect behavior. Remember to use blocking assignments for combinational logic to model immediate updates and ordered execution.