When to use blocking (combinational) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of combinational logic with blocking assignments

What is the output of the following Verilog code snippet when inputs a=1 and b=0?

Verilog

module test(input a, input b, output reg y);
  always @(*) begin
    y = a & b;
    y = y | a;
  end
endmodule

A y = 1

B y = 0

C y = x (unknown)

D Compilation error

💡 Hint

Remember blocking assignments (=) execute statements in order inside always blocks.

The first assignment sets y = a & b = 1 & 0 = 0. The second assignment updates y = y | a = 0 | 1 = 1. So final y is 1.

❓ Predict Output

intermediate

Effect of blocking vs non-blocking in combinational logic

Given the following Verilog code, what is the value of y after execution if a=1 and b=0?

Verilog

module test(input a, input b, output reg y);
  always @(*) begin
    y <= a & b;
    y <= y | a;
  end
endmodule

A y = 0

B y = 1

C Simulation error

D y = x (unknown)

💡 Hint

Non-blocking assignments (<=) update variables at the end of the time step.

The first assignment schedules y to 0. The second assignment overrides the schedule with old y | a, where old y is the previous value (unknown), resulting in y = x (unknown).

🧠 Conceptual

advanced

Why use blocking assignments for combinational logic?

Which reason best explains why blocking assignments (=) are preferred for combinational logic in Verilog?

A Because blocking assignments automatically infer flip-flops.

B Because blocking assignments delay updates until the end of the time step.

C Because blocking assignments execute sequentially, reflecting combinational logic behavior accurately.

D Because blocking assignments prevent race conditions in sequential logic.

💡 Hint

Think about how combinational logic works in hardware and how blocking assignments execute.

Blocking assignments execute statements in order immediately, which matches how combinational logic computes outputs based on inputs without delay.

🔧 Debug

advanced

Identify the problem with using non-blocking assignments in combinational logic

What issue arises if non-blocking assignments (<=) are used inside a combinational always block?

A The output may hold old values causing incorrect combinational behavior.

B The code will not compile due to syntax errors.

C The synthesis tool will infer latches instead of combinational logic.

D The simulation will run faster but produce correct results.

💡 Hint

Consider when non-blocking assignments update variables during simulation.

Non-blocking assignments update variables at the end of the time step, so outputs may not reflect input changes immediately, causing incorrect combinational simulation.

🚀 Application

expert

Determine the number of items in the resulting dictionary after combinational blocking assignments

Consider the following Verilog-like pseudocode representing combinational logic with blocking assignments: always @(*) begin for (int i = 0; i < 3; i++) begin out[i] = in[i] & enable; end end If in = {1,0,1} and enable = 1, how many elements in out will be 1 after execution?

A 3

B 2

C 1

D 0

💡 Hint

Check each bit of in ANDed with enable=1.

out[0] = 1 & 1 = 1, out[1] = 0 & 1 = 0, out[2] = 1 & 1 = 1. So two elements are 1.