When to use blocking (combinational) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a blocking assignment in Verilog?

A blocking assignment uses the '=' operator and executes statements sequentially, blocking the next statement until the current one finishes.

beginner

When should you use blocking assignments in Verilog?

Use blocking assignments for combinational logic where statements must execute in order and immediately update values within the same always block.

intermediate

Why are blocking assignments preferred for combinational logic?

Because they simulate the immediate effect of logic gates, ensuring outputs update as inputs change within the same simulation cycle.

intermediate

What can go wrong if you use non-blocking assignments in combinational logic?

Non-blocking assignments delay updates until the end of the time step, which can cause incorrect or unintended behavior in combinational circuits.

intermediate

Give an example scenario where blocking assignments are necessary.

When calculating intermediate signals step-by-step in combinational logic, blocking assignments ensure each step uses the updated value immediately.

Which assignment type should you use for combinational logic in Verilog?

A Both are equally good

B Non-blocking assignment (<=)

C Blocking assignment (=)

D Neither, use continuous assignment

Blocking assignments execute sequentially and update values immediately, which matches combinational logic behavior.

What happens if you use non-blocking assignments in combinational always blocks?

A Values update at the end of the time step

B No difference from blocking

C Simulation will fail

D Values update immediately

Non-blocking assignments delay updates until the end of the time step, which can cause incorrect combinational logic behavior.

In which type of always block is blocking assignment preferred?

A Sequential always block (@posedge clk)

B Combinational always block (@*)

C Both

D Neither

Blocking assignments are preferred in combinational always blocks to model immediate logic updates.

What operator is used for blocking assignments in Verilog?

A ==

B <=

C !=

D =

The '=' operator is used for blocking assignments.

Why is order of statements important in blocking assignments?

A Because statements execute sequentially and block the next until done

B Because all statements execute in parallel

C Order does not matter

D Statements execute randomly

Blocking assignments execute one after another, so order affects the final result.

Explain why blocking assignments are used for combinational logic in Verilog.

Think about how combinational logic updates outputs instantly when inputs change.

Describe the difference between blocking and non-blocking assignments and when to use each.

Consider how hardware behaves in combinational vs sequential circuits.