When to use blocking (combinational) in Verilog - Mini Project: Build & Apply

When to use blocking (combinational)

📖 Scenario: You are designing a simple combinational logic circuit in Verilog. You want to calculate the output based on some input signals without any delay or memory effect.

🎯 Goal: Build a Verilog module that uses blocking assignments to implement combinational logic correctly.

📋 What You'll Learn

Create input signals a and b as 1-bit wires

Create an output signal y as a 1-bit reg

Use a combinational always block with blocking assignments

Calculate y as the AND of a and b

Print the output value in a testbench

💡 Why This Matters

🌍 Real World

Combinational logic is the foundation of digital circuits like adders, multiplexers, and decoders used in all electronic devices.

💼 Career

Understanding when to use blocking assignments is essential for hardware engineers writing Verilog code for FPGA and ASIC designs.

1

Create inputs and output signals

Create a Verilog module called and_gate with inputs a and b as 1-bit wires and output y as a 1-bit reg.

Verilog

module and_gate(input wire a, input wire b, output reg y);
// Your code here
endmodule

Hint

Define the module and declare inputs and output as specified.

2

Add combinational always block with blocking assignment

Inside the and_gate module, add an always block that is sensitive to a and b. Use blocking assignment = to assign y the AND of a and b.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        // Your code here
    end
endmodule

Hint

Use blocking assignment = inside the always block for combinational logic.

3

Create a testbench to check output

Create a testbench module called testbench. Declare a and b as reg and y as wire. Instantiate and_gate with these signals. Initialize a and b to 0.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        y = a & b;
    end
endmodule

module testbench;
    // Your code here
endmodule

Hint

Instantiate the module and initialize inputs in the testbench.

4

Display output values in testbench

In the testbench, add code inside initial to display the values of a, b, and y using $monitor. Change a and b to 1 and 0, then 1 and 1 with delays.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        y = a & b;
    end
endmodule

module testbench;
    reg a, b;
    wire y;
    and_gate uut(.a(a), .b(b), .y(y));
    initial begin
        a = 0; b = 0;
        // Your code here
    end
endmodule

Hint

Use $monitor to print signal values and delays #10 to change inputs.

Practice

1. Which type of assignment should you use inside an always @(*) block to model combinational logic in Verilog?

easy

A. Continuous assignment (assign)

B. Non-blocking assignment (<=)

C. Blocking assignment (=)

D. Initial assignment

Solution

1. Step 1: Understand the purpose of always @(*) blocks

   These blocks are used to describe combinational logic where outputs depend immediately on inputs.

2. Step 2: Choose the correct assignment type for combinational logic

   Blocking assignments (=) execute statements sequentially and update values immediately, which is suitable for combinational logic.

3. Final Answer:

   Blocking assignment (=) -> Option C

4. Quick Check:

   Combinational logic uses blocking (=) [OK]

Hint: Use '=' in always @(*) for immediate updates [OK]

Common Mistakes:

• Using non-blocking (<=) in combinational blocks
• Confusing continuous assign with blocking inside always
• Using initial blocks for combinational logic

2. Which of the following is the correct syntax for a blocking assignment inside an always @(*) block?

easy

A. output <= input + 1;

B. output = input + 1;

C. assign output = input + 1;

D. initial output = input + 1;

Solution

1. Step 1: Identify the assignment type inside always @(*)

   Blocking assignments use the '=' operator inside procedural blocks.

2. Step 2: Match the syntax with blocking assignment

   The statement output = input + 1; uses '=' which is the blocking assignment syntax.

3. Final Answer:

   output = input + 1; -> Option B

4. Quick Check:

   Blocking assignment uses '=' inside always blocks [OK]

Hint: Inside always @(*), use '=' for blocking assignments [OK]

Common Mistakes:

• Using '<=' instead of '=' inside always @(*)
• Using 'assign' inside procedural blocks
• Using 'initial' for combinational logic

3. What is the output of the following Verilog code snippet?

reg a, b, c;
always @(*) begin
  a = 1'b0;
  b = a;
  c = b;
end

medium

A. a=0, b=0, c=0

B. a=0, b=1, c=1

C. a=1, b=0, c=0

D. a=1, b=1, c=1

Solution

1. Step 1: Trace the blocking assignments sequentially

   First, a = 0; sets a to 0 immediately. Then b = a; assigns b the current value of a, which is 0. Finally, c = b; assigns c the current value of b, which is 0.

2. Step 2: Confirm all variables have value 0

   All three variables a, b, and c are assigned 0 in order.

3. Final Answer:

   a=0, b=0, c=0 -> Option A

4. Quick Check:

   Blocking assignments update immediately, so all zero [OK]

Hint: Blocking updates happen immediately in order [OK]

Common Mistakes:

• Assuming b or c keep old values
• Confusing blocking with non-blocking timing
• Ignoring sequential order of assignments

4. Identify the error in this combinational logic block:

always @(*) begin
  out <= in1 & in2;
  out2 = out | in3;
end

medium

A. Using non-blocking (<=) and blocking (=) mixed in combinational block

B. Missing sensitivity list

C. Using continuous assignment inside always block

D. No error, code is correct

Solution

1. Step 1: Check assignment types inside always @(*)

   Combinational logic should use blocking assignments (=) consistently inside always @(*) blocks.

2. Step 2: Identify mixed assignment usage

   The code uses non-blocking (<=) for out and blocking (=) for out2, which is incorrect for combinational logic.

3. Final Answer:

   Using non-blocking (<=) and blocking (=) mixed in combinational block -> Option A

4. Quick Check:

   Combinational blocks use only blocking (=) [OK]

Hint: Use only '=' in combinational always blocks [OK]

Common Mistakes:

• Mixing <= and = inside combinational blocks
• Forgetting to use always @(*) for combinational logic
• Using continuous assign inside procedural blocks

5. You want to design a combinational logic block that calculates the maximum of two inputs a and b. Which of the following always @(*) blocks correctly uses blocking assignments to implement this?

hard

A. always @(*) begin
if (a > b)
max <= a;
else
max <= b;
end

B. always @(a or b) begin
if (a > b)
max = a;
else
max = b;
end

C. always @(a or b) begin
if (a > b)
max <= a;
else
max <= b;
end

D. always @(*) begin
if (a > b)
max = a;
else
max = b;
end

Solution

1. Step 1: Confirm the sensitivity list for combinational logic

   Using always @(*) is preferred for combinational logic to automatically include all inputs.

2. Step 2: Check assignment type for combinational logic

   Blocking assignments (=) must be used inside always @(*) blocks for combinational logic.

3. Step 3: Evaluate each option

   always @(*) begin if (a > b) max = a; else max = b; end uses always @(*) and blocking assignments (=), correctly modeling combinational max logic.

4. Final Answer:

   always @(*) begin if (a > b) max = a; else max = b; end -> Option D

5. Quick Check:

   Combinational max needs always @(*) and '=' [OK]

Hint: Use always @(*) with '=' for combinational max logic [OK]

Common Mistakes:

• Using non-blocking (<=) in combinational always blocks
• Using explicit sensitivity list instead of @(*)
• Mixing blocking and non-blocking assignments