When to use blocking (combinational) in Verilog - Mini Project: Build & Apply

When to use blocking (combinational)

📖 Scenario: You are designing a simple combinational logic circuit in Verilog. You want to calculate the output based on some input signals without any delay or memory effect.

🎯 Goal: Build a Verilog module that uses blocking assignments to implement combinational logic correctly.

📋 What You'll Learn

Create input signals a and b as 1-bit wires

Create an output signal y as a 1-bit reg

Use a combinational always block with blocking assignments

Calculate y as the AND of a and b

Print the output value in a testbench

💡 Why This Matters

🌍 Real World

Combinational logic is the foundation of digital circuits like adders, multiplexers, and decoders used in all electronic devices.

💼 Career

Understanding when to use blocking assignments is essential for hardware engineers writing Verilog code for FPGA and ASIC designs.

1

Create inputs and output signals

Create a Verilog module called and_gate with inputs a and b as 1-bit wires and output y as a 1-bit reg.

Verilog

module and_gate(input wire a, input wire b, output reg y);
// Your code here
endmodule

Need a hint?

Define the module and declare inputs and output as specified.

2

Add combinational always block with blocking assignment

Inside the and_gate module, add an always block that is sensitive to a and b. Use blocking assignment = to assign y the AND of a and b.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        // Your code here
    end
endmodule

Need a hint?

Use blocking assignment = inside the always block for combinational logic.

3

Create a testbench to check output

Create a testbench module called testbench. Declare a and b as reg and y as wire. Instantiate and_gate with these signals. Initialize a and b to 0.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        y = a & b;
    end
endmodule

module testbench;
    // Your code here
endmodule

Need a hint?

Instantiate the module and initialize inputs in the testbench.

4

Display output values in testbench

In the testbench, add code inside initial to display the values of a, b, and y using $monitor. Change a and b to 1 and 0, then 1 and 1 with delays.

Verilog

module and_gate(input wire a, input wire b, output reg y);
    always @ (a or b) begin
        y = a & b;
    end
endmodule

module testbench;
    reg a, b;
    wire y;
    and_gate uut(.a(a), .b(b), .y(y));
    initial begin
        a = 0; b = 0;
        // Your code here
    end
endmodule

Need a hint?

Use $monitor to print signal values and delays #10 to change inputs.