Up counter design in Verilog - Step-by-Step Execution

Concept Flow - Up counter design

Start: Reset counter to 0

↓

Wait for clock rising edge

↓

Increment counter by 1

↓

Check if counter reached max

↓

Hold new value

↩Back to Wait for clock

The counter starts at zero, increments by one on each clock pulse, and resets to zero when it reaches its maximum value.

Execution Sample

Verilog

module up_counter(
  input clk,
  input reset,
  output reg [3:0] count
);
  always @(posedge clk or posedge reset) begin
    if (reset) count <= 0;
    else if (count == 4'd15) count <= 0;
    else count <= count + 1;
  end
endmodule

A 4-bit up counter that increments on each clock pulse and resets to zero when reset is high or when the count reaches 15.

Execution Table

Step	clk edge	reset	count before	count after	Action
1	rising	0	0	1	Increment count from 0 to 1
2	rising	0	1	2	Increment count from 1 to 2
3	rising	0	2	3	Increment count from 2 to 3
4	rising	1	3	0	Reset count to 0 due to reset
5	rising	0	0	1	Increment count from 0 to 1
6	rising	0	1	2	Increment count from 1 to 2
7	rising	0	2	3	Increment count from 2 to 3
8	rising	0	3	4	Increment count from 3 to 4
9	rising	0	4	5	Increment count from 4 to 5
10	rising	0	5	6	Increment count from 5 to 6
11	rising	0	6	7	Increment count from 6 to 7
12	rising	0	7	8	Increment count from 7 to 8
13	rising	0	8	9	Increment count from 8 to 9
14	rising	0	9	10	Increment count from 9 to 10
15	rising	0	10	11	Increment count from 10 to 11
16	rising	0	11	12	Increment count from 11 to 12
17	rising	0	12	13	Increment count from 12 to 13
18	rising	0	13	14	Increment count from 13 to 14
19	rising	0	14	15	Increment count from 14 to 15
20	rising	0	15	0	Overflow: count resets to 0 (4-bit max reached)

💡 Counter resets to 0 after reaching maximum 4-bit value 15, then continues counting.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	After 12	After 13	After 14	After 15	After 16	After 17	After 18	After 19	After 20
count	0	1	2	3	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	0

Key Moments - 3 Insights

Why does the counter reset to 0 when it reaches 15?

Because the counter is 4-bit wide, it can only count from 0 to 15. After 15, it overflows and resets to 0 as shown in execution_table row 20.

What happens if reset is high during a clock edge?

The counter immediately resets to 0 regardless of its previous value, as shown in execution_table row 4.

Why do we use 'posedge clk' in the always block?

Because the counter increments only on the rising edge of the clock signal, ensuring synchronous counting as shown in the concept_flow.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of count after step 5?

A 3

B 0

C 1

D 5

💡 Hint

Check the 'count after' column in execution_table row 5.

At which step does the reset signal cause the count to go to zero?

A Step 3

B Step 4

C Step 10

D Step 20

💡 Hint

Look for the row where reset is 1 in execution_table.

If the counter was 3-bit instead of 4-bit, what would happen at step 20?

A Count resets to 0 after 7

B Count resets to 0 after 15

C Count increments to 16

D Count stays at 15

💡 Hint

A 3-bit counter max value is 7, so overflow happens after 7.

Concept Snapshot

Up Counter Design in Verilog:
- Use always @(posedge clk or posedge reset) block
- If reset is high, set count to 0
- Else if count reaches max (15), reset to 0
- Else increment count by 1 on each clock rising edge
- Counter width limits max count (e.g., 4-bit max 15)
- After max, counter overflows back to 0

Full Transcript

This visual execution traces a 4-bit up counter in Verilog. The counter starts at zero and increments by one on each rising clock edge. If the reset signal is high, the counter resets to zero immediately. The counter counts from 0 up to 15, then overflows back to 0 due to its 4-bit width limit. The execution table shows each clock step, the reset state, the count before and after increment, and the action taken. The variable tracker follows the count value through each step. Key moments clarify why the counter resets at 15, how reset works, and why the clock edge is used. The quiz tests understanding of count values at specific steps and the effect of reset and bit width. The snapshot summarizes the Verilog code pattern for an up counter.

Practice

1. What does an up counter do in Verilog?

easy

A. It holds the value constant regardless of clock.

B. It decreases its value by 1 on each clock pulse.

C. It resets the value to zero on each clock pulse.

D. It increases its value by 1 on each clock pulse.

Solution

1. Step 1: Understand the function of an up counter

   An up counter increments its stored value by 1 every time the clock signal pulses.

2. Step 2: Compare options with the definition

   Only It increases its value by 1 on each clock pulse. describes increasing the value by 1 on each clock pulse, which matches the up counter behavior.

3. Final Answer:

   It increases its value by 1 on each clock pulse. -> Option D

4. Quick Check:

   Up counter = increments by 1 [OK]

Hint: Up counter always counts up by 1 each clock pulse [OK]

Common Mistakes:

• Confusing up counter with down counter
• Thinking reset happens every clock pulse
• Assuming counter holds value without change

2. Which of the following is the correct Verilog syntax to define a 4-bit up counter with synchronous reset?

easy

A. always @(negedge clk) if (reset) count = 0; else count = count + 1;

B. always @(posedge clk) if (reset) count <= 0; else count <= count + 1;

C. always @(posedge clk) if (reset) count = 0; else count = count - 1;

D. always @(posedge clk) if (reset) count <= 1; else count <= count + 1;

Solution

1. Step 1: Identify correct clock edge and reset behavior

   Up counters usually update on the positive edge of the clock and reset synchronously to zero.

2. Step 2: Check assignment operators and counting direction

   Non-blocking assignment '<=' is preferred in sequential logic. Counting up means adding 1, and reset sets count to 0.

3. Final Answer:

   always @(posedge clk) if (reset) count <= 0; else count <= count + 1; -> Option B

4. Quick Check:

   posedge + non-blocking + reset to 0 + count up = A [OK]

Hint: Use posedge clk and non-blocking <= for counters [OK]

Common Mistakes:

• Using negedge instead of posedge
• Using blocking '=' in sequential logic
• Resetting count to 1 instead of 0
• Counting down instead of up

3. What will be the output sequence of a 3-bit up counter starting from 0 after 5 clock pulses (assuming reset is inactive)?

module counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk) begin
    if (reset) count <= 0;
    else count <= count + 1;
  end
endmodule

medium

A. [0, 1, 2, 3, 4]

B. [1, 2, 3, 4, 5]

C. [1, 2, 3, 4, 0]

D. [0, 1, 2, 3, 4, 5]

Solution

1. Step 1: Understand initial value and counting

   The counter starts at 0 after reset. On first clock pulse, count increments to 1.

2. Step 2: List values after each clock pulse

   After 1st pulse: 1, 2nd: 2, 3rd: 3, 4th: 4, 5th: 5.

3. Step 3: Consider 3-bit counter wrap-around

   Since it's a 3-bit counter, it counts from 0 to 7 and then wraps around. After 5 pulses starting from 0, the sequence is [1, 2, 3, 4, 5]. However, the question asks for the output sequence starting from 0 after 5 pulses, which includes the initial 0 and the next 4 increments: [0, 1, 2, 3, 4].

4. Final Answer:

   [0, 1, 2, 3, 4] -> Option A

5. Quick Check:

   Count starts at 0, increments each pulse = [0..4] [OK]

Hint: Count increments after clock pulse, starts from 0 [OK]

Common Mistakes:

• Including initial 0 before first pulse
• Counting 6 values instead of 5
• Confusing count start value

4. Identify the error in this Verilog code for a 4-bit up counter:

module counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset == 1) count = 0;
    else count = count + 1;
  end
endmodule

medium

A. Output 'count' should not be declared as reg.

B. Reset condition should be 'if (reset != 1)'.

C. Using blocking assignments '=' instead of non-blocking '<=' inside always block.

D. Clock edge sensitivity should be negedge instead of posedge.

Solution

1. Step 1: Check assignment type in sequential always block

   Inside always @(posedge clk), non-blocking assignments '<=' should be used to avoid race conditions.

2. Step 2: Verify other parts of the code

   Reset condition and reg declaration are correct. Clock edge is correctly posedge.

3. Final Answer:

   Using blocking assignments '=' instead of non-blocking '<=' inside always block. -> Option C

4. Quick Check:

   Sequential logic uses '<=' not '=' [OK]

Hint: Use '<=' for sequential logic assignments [OK]

Common Mistakes:

• Using '=' in always @(posedge clk)
• Misunderstanding reset condition
• Thinking reg is wrong for output
• Changing clock edge unnecessarily

5. How can you modify a 4-bit up counter to count only when an enable signal is high?

module counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset) count <= 0;
    else count <= count + 1;
  end
endmodule

hard

A. Add 'if (enable) count <= count + 1;' inside the always block after reset check.

B. Add 'if (enable) count = count + 1;' outside the always block.

C. Replace 'count <= count + 1;' with 'count <= count - 1;' when enable is high.

D. Add 'enable' to the sensitivity list of the always block.

Solution

1. Step 1: Understand how to control counting with enable

   Counting should happen only when enable is high, so add a condition inside the always block after reset.

2. Step 2: Implement enable check correctly

   Use 'if (enable) count <= count + 1;' with non-blocking assignment inside the always block.

3. Final Answer:

   Add 'if (enable) count <= count + 1;' inside the always block after reset check. -> Option A

4. Quick Check:

   Enable controls counting inside always block [OK]

Hint: Check enable inside always block after reset [OK]

Common Mistakes:

• Using blocking assignment outside always block
• Changing count direction instead of gating
• Adding enable to sensitivity list (not needed)