Up counter design in Verilog - Mini Project: Build & Apply

Up Counter Design in Verilog

📖 Scenario: You are designing a simple digital up counter for a small device. This counter will count from 0 upwards each time a clock pulse arrives.

🎯 Goal: Build a Verilog module that counts up by 1 on each clock pulse and resets to 0 when a reset signal is active.

📋 What You'll Learn

Create a 4-bit register to hold the count

Use a clock and reset input

Increment the count on the rising edge of the clock

Reset the count to 0 when reset is high

Display the count value

💡 Why This Matters

🌍 Real World

Up counters are used in digital clocks, timers, and event counters in many electronic devices.

💼 Career

Understanding counters is fundamental for hardware design engineers working with digital circuits and FPGA programming.

1

Create the module and declare inputs and outputs

Write a Verilog module named up_counter with inputs clk and reset, and a 4-bit output count. Declare count as a reg type.

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);
// Your code here
endmodule

Need a hint?

Start by defining the module and its ports exactly as described.

2

Initialize the count register

Inside the up_counter module, declare an always block triggered on the rising edge of clk or when reset is high. Inside it, set count to 0 if reset is high.

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    // Your code here
end

endmodule

Need a hint?

Use a non-blocking assignment to set count to zero when reset is high.

3

Add the counting logic

In the same always block, add an else clause that increments count by 1 on each rising clock edge.

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 4'b0000;
    end else begin
        // Your code here
    end
end

endmodule

Need a hint?

Increment count by 1 using a non-blocking assignment inside the else block.

4

Test and display the count value

Add a testbench module named testbench that instantiates up_counter. Generate a clock signal that toggles every 5 time units. Apply a reset pulse for 10 time units at the start. Run the simulation for 50 time units and use $display to print the count value at each positive clock edge.

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 4'b0000;
    end else begin
        count <= count + 1;
    end
end

endmodule

// Your testbench code here

Need a hint?

Create a testbench that toggles the clock every 5 time units, applies reset for 10 time units, and prints the count on each clock rising edge.