Up counter design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register named 'count'.

Verilog

reg [3:0] [1] ;

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Aclk

Bcount

Creset

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using signal names like 'clk' or 'reset' instead of the counter register.

The 4-bit register to hold the counter value is named 'count'.

2fill in blank

medium

Complete the code to increment the counter on the rising edge of the clock.

Verilog

always @(posedge [1]) begin
    count <= count + 1;
end

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Acount

Breset

Cenable

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' or 'enable' instead of 'clk' in the sensitivity list.

The counter increments on the rising edge of the clock signal 'clk'.

3fill in blank

hard

Fix the error in the reset condition to asynchronously reset the counter to zero.

Verilog

always @(posedge clk or posedge [1]) begin
    if (reset) begin
        count <= 0;
    end else begin
        count <= count + 1;
    end
end

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Aenable

Bclk

Creset

Dcount

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' or 'enable' instead of 'reset' in the sensitivity list.

The asynchronous reset triggers on the positive edge of the 'reset' signal.

4fill in blank

hard

Fill in the blank to complete the synchronous enable logic for the counter.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        count <= count + 1;
    end else begin
        count <= count;
    end
end

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Aenable

Breset

Cclk

Dcount

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' or 'clk' in the if condition instead of 'enable'.

The counter increments only when 'enable' is high; otherwise, it holds its value.

5fill in blank

hard

Fill all three blanks to complete the counter with synchronous reset and enable.

Verilog

always @(posedge clk) begin
    if ([1]) begin
        count <= 0;
    end else if ([2]) begin
        count <= count [3] 1;
    end else begin
        count <= count;
    end
end

Drag options to blanks, or click blank then click option'

Areset

Benable

C+

D-

Attempts:

3 left

💡 Hint

Common Mistakes

Using '-' instead of '+' for increment.

Mixing up 'reset' and 'enable' signals.

The counter resets to zero when 'reset' is high; otherwise, it increments by 1 when 'enable' is high.