Up counter design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit synchronous up counter

What is the output of the 4-bit synchronous up counter after 5 clock pulses if it starts from 4'b0000?

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 4'b0000;
    else
      count <= count + 1;
  end
endmodule

A 4'b0101

B 4'b0100

C 4'b0110

D 4'b0011

💡 Hint

Count increments by 1 on each clock pulse starting from zero after reset.

The counter starts at 0 and increments by 1 each clock pulse. After 5 pulses, the count is 5 in binary 0101.

🧠 Conceptual

intermediate

Understanding asynchronous reset in up counters

What is the main effect of using an asynchronous reset in an up counter design?

A The counter resets only on the next clock edge after reset is asserted.

B The counter ignores the reset signal during counting.

C The counter counts down instead of up when reset is asserted.

D The counter resets immediately when reset is asserted, regardless of the clock.

💡 Hint

Asynchronous means it does not wait for the clock.

An asynchronous reset forces the counter to reset immediately when the reset signal is active, without waiting for a clock edge.

🔧 Debug

advanced

Identify the error in this up counter code

What error will this Verilog code produce when synthesized or simulated?

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset == 1)
      count = 4'b0000;
    else
      count = count + 1;
  end
endmodule

A No error, code works correctly.

B Runtime error because count is not initialized.

C Synthesis error due to missing non-blocking assignments.

D Syntax error due to missing semicolon.

💡 Hint

Consider the difference between blocking (=) and non-blocking (<=) assignments in sequential logic.

In sequential always blocks triggered by clock edges, non-blocking assignments (<=) must be used to avoid race conditions and synthesis errors.

📝 Syntax

advanced

Syntax error in up counter sensitivity list

Which option correctly fixes the sensitivity list for an asynchronous reset in this up counter?

Verilog

always @(posedge clk or reset) begin
  if (reset)
    count <= 0;
  else
    count <= count + 1;
end

A always @(posedge clk and posedge reset) begin

B always @(posedge clk or posedge reset) begin

C always @(clk or reset) begin

D always @(negedge clk or posedge reset) begin

💡 Hint

Asynchronous reset sensitivity must be on the positive edge of reset signal.

The sensitivity list must include posedge clk and posedge reset to detect clock rising edge and asynchronous reset activation.

🚀 Application

expert

Number of states in a 5-bit up counter

How many unique states does a 5-bit up counter cycle through before repeating?

A 32

B 10

C 64

D 16

💡 Hint

Number of states is 2 raised to the number of bits.

A 5-bit counter can represent 2^5 = 32 unique states from 0 to 31.

Practice

1. What does an up counter do in Verilog?

easy

A. It holds the value constant regardless of clock.

B. It decreases its value by 1 on each clock pulse.

C. It resets the value to zero on each clock pulse.

D. It increases its value by 1 on each clock pulse.

Solution

1. Step 1: Understand the function of an up counter

   An up counter increments its stored value by 1 every time the clock signal pulses.

2. Step 2: Compare options with the definition

   Only It increases its value by 1 on each clock pulse. describes increasing the value by 1 on each clock pulse, which matches the up counter behavior.

3. Final Answer:

   It increases its value by 1 on each clock pulse. -> Option D

4. Quick Check:

   Up counter = increments by 1 [OK]

Hint: Up counter always counts up by 1 each clock pulse [OK]

Common Mistakes:

• Confusing up counter with down counter
• Thinking reset happens every clock pulse
• Assuming counter holds value without change

2. Which of the following is the correct Verilog syntax to define a 4-bit up counter with synchronous reset?

easy

A. always @(negedge clk) if (reset) count = 0; else count = count + 1;

B. always @(posedge clk) if (reset) count <= 0; else count <= count + 1;

C. always @(posedge clk) if (reset) count = 0; else count = count - 1;

D. always @(posedge clk) if (reset) count <= 1; else count <= count + 1;

Solution

1. Step 1: Identify correct clock edge and reset behavior

   Up counters usually update on the positive edge of the clock and reset synchronously to zero.

2. Step 2: Check assignment operators and counting direction

   Non-blocking assignment '<=' is preferred in sequential logic. Counting up means adding 1, and reset sets count to 0.

3. Final Answer:

   always @(posedge clk) if (reset) count <= 0; else count <= count + 1; -> Option B

4. Quick Check:

   posedge + non-blocking + reset to 0 + count up = A [OK]

Hint: Use posedge clk and non-blocking <= for counters [OK]

Common Mistakes:

• Using negedge instead of posedge
• Using blocking '=' in sequential logic
• Resetting count to 1 instead of 0
• Counting down instead of up

3. What will be the output sequence of a 3-bit up counter starting from 0 after 5 clock pulses (assuming reset is inactive)?

module counter(input clk, input reset, output reg [2:0] count);
  always @(posedge clk) begin
    if (reset) count <= 0;
    else count <= count + 1;
  end
endmodule

medium

A. [0, 1, 2, 3, 4]

B. [1, 2, 3, 4, 5]

C. [1, 2, 3, 4, 0]

D. [0, 1, 2, 3, 4, 5]

Solution

1. Step 1: Understand initial value and counting

   The counter starts at 0 after reset. On first clock pulse, count increments to 1.

2. Step 2: List values after each clock pulse

   After 1st pulse: 1, 2nd: 2, 3rd: 3, 4th: 4, 5th: 5.

3. Step 3: Consider 3-bit counter wrap-around

   Since it's a 3-bit counter, it counts from 0 to 7 and then wraps around. After 5 pulses starting from 0, the sequence is [1, 2, 3, 4, 5]. However, the question asks for the output sequence starting from 0 after 5 pulses, which includes the initial 0 and the next 4 increments: [0, 1, 2, 3, 4].

4. Final Answer:

   [0, 1, 2, 3, 4] -> Option A

5. Quick Check:

   Count starts at 0, increments each pulse = [0..4] [OK]

Hint: Count increments after clock pulse, starts from 0 [OK]

Common Mistakes:

• Including initial 0 before first pulse
• Counting 6 values instead of 5
• Confusing count start value

4. Identify the error in this Verilog code for a 4-bit up counter:

module counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset == 1) count = 0;
    else count = count + 1;
  end
endmodule

medium

A. Output 'count' should not be declared as reg.

B. Reset condition should be 'if (reset != 1)'.

C. Using blocking assignments '=' instead of non-blocking '<=' inside always block.

D. Clock edge sensitivity should be negedge instead of posedge.

Solution

1. Step 1: Check assignment type in sequential always block

   Inside always @(posedge clk), non-blocking assignments '<=' should be used to avoid race conditions.

2. Step 2: Verify other parts of the code

   Reset condition and reg declaration are correct. Clock edge is correctly posedge.

3. Final Answer:

   Using blocking assignments '=' instead of non-blocking '<=' inside always block. -> Option C

4. Quick Check:

   Sequential logic uses '<=' not '=' [OK]

Hint: Use '<=' for sequential logic assignments [OK]

Common Mistakes:

• Using '=' in always @(posedge clk)
• Misunderstanding reset condition
• Thinking reg is wrong for output
• Changing clock edge unnecessarily

5. How can you modify a 4-bit up counter to count only when an enable signal is high?

module counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset) count <= 0;
    else count <= count + 1;
  end
endmodule

hard

A. Add 'if (enable) count <= count + 1;' inside the always block after reset check.

B. Add 'if (enable) count = count + 1;' outside the always block.

C. Replace 'count <= count + 1;' with 'count <= count - 1;' when enable is high.

D. Add 'enable' to the sensitivity list of the always block.

Solution

1. Step 1: Understand how to control counting with enable

   Counting should happen only when enable is high, so add a condition inside the always block after reset.

2. Step 2: Implement enable check correctly

   Use 'if (enable) count <= count + 1;' with non-blocking assignment inside the always block.

3. Final Answer:

   Add 'if (enable) count <= count + 1;' inside the always block after reset check. -> Option A

4. Quick Check:

   Enable controls counting inside always block [OK]

Hint: Check enable inside always block after reset [OK]

Common Mistakes:

• Using blocking assignment outside always block
• Changing count direction instead of gating
• Adding enable to sensitivity list (not needed)