Up counter design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit synchronous up counter

What is the output of the 4-bit synchronous up counter after 5 clock pulses if it starts from 4'b0000?

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 4'b0000;
    else
      count <= count + 1;
  end
endmodule

A 4'b0101

B 4'b0100

C 4'b0110

D 4'b0011

💡 Hint

Count increments by 1 on each clock pulse starting from zero after reset.

The counter starts at 0 and increments by 1 each clock pulse. After 5 pulses, the count is 5 in binary 0101.

🧠 Conceptual

intermediate

Understanding asynchronous reset in up counters

What is the main effect of using an asynchronous reset in an up counter design?

A The counter resets only on the next clock edge after reset is asserted.

B The counter ignores the reset signal during counting.

C The counter counts down instead of up when reset is asserted.

D The counter resets immediately when reset is asserted, regardless of the clock.

💡 Hint

Asynchronous means it does not wait for the clock.

An asynchronous reset forces the counter to reset immediately when the reset signal is active, without waiting for a clock edge.

🔧 Debug

advanced

Identify the error in this up counter code

What error will this Verilog code produce when synthesized or simulated?

Verilog

module up_counter(input clk, input reset, output reg [3:0] count);
  always @(posedge clk) begin
    if (reset == 1)
      count = 4'b0000;
    else
      count = count + 1;
  end
endmodule

A No error, code works correctly.

B Runtime error because count is not initialized.

C Synthesis error due to missing non-blocking assignments.

D Syntax error due to missing semicolon.

💡 Hint

Consider the difference between blocking (=) and non-blocking (<=) assignments in sequential logic.

In sequential always blocks triggered by clock edges, non-blocking assignments (<=) must be used to avoid race conditions and synthesis errors.

📝 Syntax

advanced

Syntax error in up counter sensitivity list

Which option correctly fixes the sensitivity list for an asynchronous reset in this up counter?

Verilog

always @(posedge clk or reset) begin
  if (reset)
    count <= 0;
  else
    count <= count + 1;
end

A always @(posedge clk and posedge reset) begin

B always @(posedge clk or posedge reset) begin

C always @(clk or reset) begin

D always @(negedge clk or posedge reset) begin

💡 Hint

Asynchronous reset sensitivity must be on the positive edge of reset signal.

The sensitivity list must include posedge clk and posedge reset to detect clock rising edge and asynchronous reset activation.

🚀 Application

expert

Number of states in a 5-bit up counter

How many unique states does a 5-bit up counter cycle through before repeating?

A 32

B 10

C 64

D 16

💡 Hint

Number of states is 2 raised to the number of bits.

A 5-bit counter can represent 2^5 = 32 unique states from 0 to 31.