Up counter design in Verilog - Time & Space Complexity

Time Complexity: Up counter design

O(n)

Understanding Time Complexity

We want to understand how the time it takes for an up counter to run grows as the count value increases.

How does the number of steps change when the counter counts higher?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module up_counter(
  input wire clk,
  input wire reset,
  output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
  if (reset)
    count <= 0;
  else
    count <= count + 1;
end
endmodule

This code defines a 4-bit up counter that increases its value by 1 on each clock pulse, resetting to zero when reset is high.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: Incrementing the count value on each clock cycle.
• How many times: Once per clock pulse, repeating continuously.

How Execution Grows With Input

Each clock pulse causes one increment operation, so the number of increments grows directly with the count value.

Input Size (n)	Approx. Operations
10	10 increments
100	100 increments
1000	1000 increments

Pattern observation: The number of operations grows in a straight line as the count increases.

Final Time Complexity

Time Complexity: O(n)

This means the time to reach a certain count grows directly with the size of that count.

Common Mistake

[X] Wrong: "The counter increments instantly for any count value, so time does not grow with count."

[OK] Correct: Each increment happens on a clock pulse, so counting higher means more pulses and more time.

Interview Connect

Understanding how counters work and how their operation time grows helps you reason about hardware timing and performance in real designs.

Self-Check

"What if we changed the counter to increment by 2 each clock cycle? How would the time complexity change?"