Traffic light controller FSM in Verilog - Step-by-Step Execution

Concept Flow - Traffic light controller FSM

Start: Reset

↓

State: Green Light

↓

Timer expires?

No→Stay Green

Yes↓

State: Yellow Light

↓

Timer expires?

No→Stay Yellow

Yes↓

State: Red Light

↓

Timer expires?

No→Stay Red

↩Back to Green Light

The traffic light FSM cycles through Green, Yellow, and Red states, each lasting a set time before moving to the next.

Execution Sample

Verilog

module traffic_light_fsm(
  input clk, reset,
  output reg [2:0] light
);
  typedef enum {GREEN, YELLOW, RED} state_t;
  state_t state = GREEN;
  // Timer logic omitted for brevity
endmodule

This Verilog FSM cycles traffic lights through Green, Yellow, and Red states on a clock with reset.

Execution Table

Step	Current State	Timer	Condition	Next State	Output Light
1	RESET	0	reset=1	GREEN	Green=1, Yellow=0, Red=0
2	GREEN	0	timer < green_time	GREEN	Green=1, Yellow=0, Red=0
3	GREEN	green_time	timer == green_time	YELLOW	Green=0, Yellow=1, Red=0
4	YELLOW	0	timer < yellow_time	YELLOW	Green=0, Yellow=1, Red=0
5	YELLOW	yellow_time	timer == yellow_time	RED	Green=0, Yellow=0, Red=1
6	RED	0	timer < red_time	RED	Green=0, Yellow=0, Red=1
7	RED	red_time	timer == red_time	GREEN	Green=1, Yellow=0, Red=0

💡 FSM cycles continuously through GREEN -> YELLOW -> RED states based on timer values.

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 5	After Step 7
state	RESET	GREEN	YELLOW	RED	GREEN
timer	0	incrementing	reset to 0	reset to 0	reset to 0
light	000	100	010	001	100

Key Moments - 3 Insights

Why does the FSM reset the timer when changing states?

The timer resets at each state change to count the duration of the new state separately, as shown in steps 3, 5, and 7 in the execution_table.

What happens if reset is active during operation?

When reset=1, the FSM immediately goes to GREEN state with timer=0 and light=Green on (step 1), overriding other states.

Why does the FSM cycle back to GREEN after RED?

The FSM is designed to cycle through states in order: GREEN -> YELLOW -> RED -> GREEN, as shown by the next state transitions in the execution_table rows 7 back to 2.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output light when the FSM is in YELLOW state at step 4?

A Green=1, Yellow=0, Red=0

B Green=0, Yellow=0, Red=1

C Green=0, Yellow=1, Red=0

D All lights off

💡 Hint

Check the Output Light column for step 4 in the execution_table.

At which step does the FSM transition from RED back to GREEN?

A Step 6

B Step 7

C Step 5

D Step 3

💡 Hint

Look at the Next State column in the execution_table for when state changes from RED to GREEN.

If the timer did not reset after changing from GREEN to YELLOW, what would happen?

A The FSM timer would count incorrectly causing wrong state durations

B The FSM would stay in YELLOW indefinitely

C The FSM would skip YELLOW and go to RED immediately

D The FSM would reset to GREEN immediately

💡 Hint

Refer to the key_moments about timer reset and the variable_tracker showing timer resets at state changes.

Concept Snapshot

Traffic Light FSM in Verilog:
- States: GREEN, YELLOW, RED
- Timer counts duration per state
- On timer expiry, move to next state
- Reset sets state to GREEN
- Output controls lights accordingly

Full Transcript

This traffic light controller FSM cycles through three states: GREEN, YELLOW, and RED. It starts at GREEN after reset. Each state lasts a set time controlled by a timer. When the timer reaches the state's duration, the FSM moves to the next state and resets the timer. The output lights correspond to the current state. The FSM loops continuously, ensuring safe traffic light operation.