Traffic light controller FSM in Verilog - Step-by-Step Execution

Concept Flow - Traffic light controller FSM

Start: Reset

↓

State: Green Light

↓

Timer expires?

No→Stay Green

Yes↓

State: Yellow Light

↓

Timer expires?

No→Stay Yellow

Yes↓

State: Red Light

↓

Timer expires?

No→Stay Red

↩Back to Green Light

The traffic light FSM cycles through Green, Yellow, and Red states, each lasting a set time before moving to the next.

Execution Sample

Verilog

module traffic_light_fsm(
  input clk, reset,
  output reg [2:0] light
);
  typedef enum {GREEN, YELLOW, RED} state_t;
  state_t state = GREEN;
  // Timer logic omitted for brevity
endmodule

This Verilog FSM cycles traffic lights through Green, Yellow, and Red states on a clock with reset.

Execution Table

Step	Current State	Timer	Condition	Next State	Output Light
1	RESET	0	reset=1	GREEN	Green=1, Yellow=0, Red=0
2	GREEN	0	timer < green_time	GREEN	Green=1, Yellow=0, Red=0
3	GREEN	green_time	timer == green_time	YELLOW	Green=0, Yellow=1, Red=0
4	YELLOW	0	timer < yellow_time	YELLOW	Green=0, Yellow=1, Red=0
5	YELLOW	yellow_time	timer == yellow_time	RED	Green=0, Yellow=0, Red=1
6	RED	0	timer < red_time	RED	Green=0, Yellow=0, Red=1
7	RED	red_time	timer == red_time	GREEN	Green=1, Yellow=0, Red=0

💡 FSM cycles continuously through GREEN -> YELLOW -> RED states based on timer values.

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 5	After Step 7
state	RESET	GREEN	YELLOW	RED	GREEN
timer	0	incrementing	reset to 0	reset to 0	reset to 0
light	000	100	010	001	100

Key Moments - 3 Insights

Why does the FSM reset the timer when changing states?

The timer resets at each state change to count the duration of the new state separately, as shown in steps 3, 5, and 7 in the execution_table.

What happens if reset is active during operation?

When reset=1, the FSM immediately goes to GREEN state with timer=0 and light=Green on (step 1), overriding other states.

Why does the FSM cycle back to GREEN after RED?

The FSM is designed to cycle through states in order: GREEN -> YELLOW -> RED -> GREEN, as shown by the next state transitions in the execution_table rows 7 back to 2.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output light when the FSM is in YELLOW state at step 4?

A Green=1, Yellow=0, Red=0

B Green=0, Yellow=0, Red=1

C Green=0, Yellow=1, Red=0

D All lights off

💡 Hint

Check the Output Light column for step 4 in the execution_table.

At which step does the FSM transition from RED back to GREEN?

A Step 6

B Step 7

C Step 5

D Step 3

💡 Hint

Look at the Next State column in the execution_table for when state changes from RED to GREEN.

If the timer did not reset after changing from GREEN to YELLOW, what would happen?

A The FSM timer would count incorrectly causing wrong state durations

B The FSM would stay in YELLOW indefinitely

C The FSM would skip YELLOW and go to RED immediately

D The FSM would reset to GREEN immediately

💡 Hint

Refer to the key_moments about timer reset and the variable_tracker showing timer resets at state changes.

Concept Snapshot

Traffic Light FSM in Verilog:
- States: GREEN, YELLOW, RED
- Timer counts duration per state
- On timer expiry, move to next state
- Reset sets state to GREEN
- Output controls lights accordingly

Full Transcript

This traffic light controller FSM cycles through three states: GREEN, YELLOW, and RED. It starts at GREEN after reset. Each state lasts a set time controlled by a timer. When the timer reaches the state's duration, the FSM moves to the next state and resets the timer. The output lights correspond to the current state. The FSM loops continuously, ensuring safe traffic light operation.

Practice

1. What is the main purpose of a traffic light controller FSM in Verilog?

easy

A. To detect traffic jams using sensors

B. To count the number of cars passing the intersection

C. To change traffic lights in a safe and timed sequence

D. To control the speed of vehicles on the road

Solution

1. Step 1: Understand FSM role in traffic lights

   A traffic light controller FSM manages the sequence of lights (red, yellow, green) safely and in timed order.

2. Step 2: Compare options to FSM purpose

   Only To change traffic lights in a safe and timed sequence describes changing lights in a safe and timed sequence, which is the FSM's job.

3. Final Answer:

   To change traffic lights in a safe and timed sequence -> Option C

4. Quick Check:

   FSM controls light sequence = A [OK]

Hint: FSM controls states and timing for lights [OK]

Common Mistakes:

• Confusing FSM with sensor or speed control
• Thinking FSM counts cars
• Assuming FSM controls vehicle speed

2. Which Verilog code snippet correctly declares the state variable for a traffic light FSM?

easy

A. logic state; // single bit logic variable

B. wire state; // single wire for state

C. integer state = 0; // integer state variable

D. reg [1:0] state; // 2-bit state variable

Solution

1. Step 1: Identify correct state variable type

   FSM states are stored in registers (reg) because they hold values across clock cycles.

2. Step 2: Check bit width for multiple states

   Traffic light FSM usually needs multiple bits (e.g., 2 bits) to represent states, so reg [1:0] is correct.

3. Final Answer:

   reg [1:0] state; // 2-bit state variable -> Option D

4. Quick Check:

   State needs reg and multiple bits = A [OK]

Hint: Use reg with enough bits for states [OK]

Common Mistakes:

• Using wire instead of reg for state
• Using single bit for multiple states
• Using integer without clocked assignment

3. Given this Verilog snippet for a traffic light FSM state transition:

always @(posedge clk) begin
  case(state)
    2'b00: state <= 2'b01;
    2'b01: state <= 2'b10;
    2'b10: state <= 2'b00;
    default: state <= 2'b00;
  endcase
end

What will be the sequence of states after 4 clock cycles starting from 2'b00?

medium

A. 00, 01, 10, 00

B. 00, 10, 01, 00

C. 00, 01, 00, 10

D. 00, 10, 10, 01

Solution

1. Step 1: Trace state transitions step-by-step

   Start at 00, next is 01, then 10, then back to 00 on each clock.

2. Step 2: List states for 4 cycles

   Cycle 1: 00, Cycle 2: 01, Cycle 3: 10, Cycle 4: 00.

3. Final Answer:

   00, 01, 10, 00 -> Option A

4. Quick Check:

   Follow case transitions = B [OK]

Hint: Follow case transitions in order [OK]

Common Mistakes:

• Mixing up state assignments order
• Forgetting default case resets state
• Assuming states skip steps

4. Identify the error in this Verilog FSM snippet for a traffic light controller:

always @(posedge clk) begin
  if (reset) state <= 2'b00;
  else
    case(state)
      2'b00: state = 2'b01;
      2'b01: state = 2'b10;
      2'b10: state = 2'b00;
    endcase
end

medium

A. Using blocking assignment (=) inside sequential always block

B. Missing default case in case statement

C. Reset condition should be asynchronous

D. State variable declared as wire instead of reg

Solution

1. Step 1: Check assignment types in clocked always block

   Inside always @(posedge clk), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify incorrect use of blocking assignment

   The code uses '=' (blocking) inside sequential logic, which is incorrect.

3. Final Answer:

   Using blocking assignment (=) inside sequential always block -> Option A

4. Quick Check:

   Use non-blocking (<=) in clocked blocks = C [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Ignoring missing default case (less critical)
• Confusing synchronous and asynchronous reset

5. You want to add a pedestrian crossing state to a traffic light FSM with states: Green (00), Yellow (01), Red (10), and Pedestrian Walk (11). Which state transition sequence correctly includes the pedestrian state after Red?

hard

A. Pedestrian Walk (11) -> Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11)

B. Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00)

C. Green (00) -> Yellow (01) -> Pedestrian Walk (11) -> Red (10) -> Green (00)

D. Green (00) -> Pedestrian Walk (11) -> Yellow (01) -> Red (10) -> Green (00)

Solution

1. Step 1: Understand safe traffic light sequence

   Normal sequence is Green -> Yellow -> Red, then pedestrian walk should come after Red for safety.

2. Step 2: Check options for correct order

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) correctly places Pedestrian Walk after Red, then cycles back to Green.

3. Final Answer:

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) -> Option B

4. Quick Check:

   Pedestrian after Red before Green = D [OK]

Hint: Pedestrian walk follows Red light for safety [OK]

Common Mistakes:

• Placing pedestrian walk before Yellow or Green
• Skipping pedestrian state in sequence
• Looping pedestrian state incorrectly