Traffic light controller FSM in Verilog - Mini Project: Build & Apply

Traffic Light Controller FSM

📖 Scenario: You are designing a simple traffic light controller for a crossroad. The traffic light cycles through green, yellow, and red lights in a fixed order to control the traffic flow safely.

🎯 Goal: Build a Verilog module that implements a traffic light controller using a finite state machine (FSM). The FSM will cycle through three states: green, yellow, and red. Each state will last for a fixed number of clock cycles.

📋 What You'll Learn

Create a Verilog module named traffic_light_controller with inputs clk and reset.

Define three states: GREEN, YELLOW, and RED using an enum.

Use a state register to hold the current state and a counter to count clock cycles for timing.

Cycle through the states in order: GREEN → YELLOW → RED → GREEN.

Output signals green_light, yellow_light, and red_light should be high only in their respective states.

💡 Why This Matters

🌍 Real World

Traffic light controllers are used in real intersections to manage vehicle and pedestrian traffic safely and efficiently.

💼 Career

Understanding FSM design in Verilog is essential for hardware engineers working on embedded systems, digital design, and FPGA programming.

1

Define the module and states

Create a Verilog module named traffic_light_controller with inputs clk and reset. Inside the module, define an enum type called state_t with three states: GREEN, YELLOW, and RED. Declare a variable state of type state_t to hold the current state.

Verilog

module traffic_light_controller(input clk, input reset);

// Define the states using enum
// Your code here

endmodule

Hint

Use typedef enum logic [1:0] to define the states and declare a variable state of that type.

2

Add a counter for timing

Inside the traffic_light_controller module, declare a 4-bit register called counter to count clock cycles for timing the states. Initialize it to zero.

Verilog

module traffic_light_controller(input clk, input reset);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    // Declare a 4-bit counter register
    // Your code here

endmodule

Hint

Use reg [3:0] counter = 4'd0; to declare and initialize the counter.

3

Implement the FSM state transitions

Add an always_ff block triggered on the rising edge of clk or when reset is high. Inside, if reset is high, set state to GREEN and counter to zero. Otherwise, increment counter. When counter reaches 4, reset it to zero and change state to the next state in the order: GREEN → YELLOW → RED → GREEN.

Verilog

module traffic_light_controller(input clk, input reset);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    reg [3:0] counter = 4'd0;

    // Add always_ff block for state transitions
    // Your code here

endmodule

Hint

Use always_ff @(posedge clk or posedge reset) and a case statement to handle state changes.

4

Output the traffic light signals

Declare three output registers: green_light, yellow_light, and red_light. Use a combinational always_comb block to set these outputs high only when the state matches their color. Then, add output reg green_light, yellow_light, red_light to the module ports. Finally, print the current state name as a string using $display inside the always_ff block after state changes.

Verilog

module traffic_light_controller(input clk, input reset, output reg green_light, output reg yellow_light, output reg red_light);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    reg [3:0] counter = 4'd0;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= GREEN;
            counter <= 4'd0;
        end else begin
            if (counter == 4'd4) begin
                counter <= 4'd0;
                case (state)
                    GREEN: state <= YELLOW;
                    YELLOW: state <= RED;
                    RED: state <= GREEN;
                    default: state <= GREEN;
                endcase
            end else begin
                counter <= counter + 1;
            end
        end
    end

    // Add always_comb block to set output lights
    // Your code here

endmodule

Hint

Use always_comb to set the outputs based on the current state. Use $display to print the state name after each change.

Practice

1. What is the main purpose of a traffic light controller FSM in Verilog?

easy

A. To detect traffic jams using sensors

B. To count the number of cars passing the intersection

C. To change traffic lights in a safe and timed sequence

D. To control the speed of vehicles on the road

Solution

1. Step 1: Understand FSM role in traffic lights

   A traffic light controller FSM manages the sequence of lights (red, yellow, green) safely and in timed order.

2. Step 2: Compare options to FSM purpose

   Only To change traffic lights in a safe and timed sequence describes changing lights in a safe and timed sequence, which is the FSM's job.

3. Final Answer:

   To change traffic lights in a safe and timed sequence -> Option C

4. Quick Check:

   FSM controls light sequence = A [OK]

Hint: FSM controls states and timing for lights [OK]

Common Mistakes:

• Confusing FSM with sensor or speed control
• Thinking FSM counts cars
• Assuming FSM controls vehicle speed

2. Which Verilog code snippet correctly declares the state variable for a traffic light FSM?

easy

A. logic state; // single bit logic variable

B. wire state; // single wire for state

C. integer state = 0; // integer state variable

D. reg [1:0] state; // 2-bit state variable

Solution

1. Step 1: Identify correct state variable type

   FSM states are stored in registers (reg) because they hold values across clock cycles.

2. Step 2: Check bit width for multiple states

   Traffic light FSM usually needs multiple bits (e.g., 2 bits) to represent states, so reg [1:0] is correct.

3. Final Answer:

   reg [1:0] state; // 2-bit state variable -> Option D

4. Quick Check:

   State needs reg and multiple bits = A [OK]

Hint: Use reg with enough bits for states [OK]

Common Mistakes:

• Using wire instead of reg for state
• Using single bit for multiple states
• Using integer without clocked assignment

3. Given this Verilog snippet for a traffic light FSM state transition:

always @(posedge clk) begin
  case(state)
    2'b00: state <= 2'b01;
    2'b01: state <= 2'b10;
    2'b10: state <= 2'b00;
    default: state <= 2'b00;
  endcase
end

What will be the sequence of states after 4 clock cycles starting from 2'b00?

medium

A. 00, 01, 10, 00

B. 00, 10, 01, 00

C. 00, 01, 00, 10

D. 00, 10, 10, 01

Solution

1. Step 1: Trace state transitions step-by-step

   Start at 00, next is 01, then 10, then back to 00 on each clock.

2. Step 2: List states for 4 cycles

   Cycle 1: 00, Cycle 2: 01, Cycle 3: 10, Cycle 4: 00.

3. Final Answer:

   00, 01, 10, 00 -> Option A

4. Quick Check:

   Follow case transitions = B [OK]

Hint: Follow case transitions in order [OK]

Common Mistakes:

• Mixing up state assignments order
• Forgetting default case resets state
• Assuming states skip steps

4. Identify the error in this Verilog FSM snippet for a traffic light controller:

always @(posedge clk) begin
  if (reset) state <= 2'b00;
  else
    case(state)
      2'b00: state = 2'b01;
      2'b01: state = 2'b10;
      2'b10: state = 2'b00;
    endcase
end

medium

A. Using blocking assignment (=) inside sequential always block

B. Missing default case in case statement

C. Reset condition should be asynchronous

D. State variable declared as wire instead of reg

Solution

1. Step 1: Check assignment types in clocked always block

   Inside always @(posedge clk), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify incorrect use of blocking assignment

   The code uses '=' (blocking) inside sequential logic, which is incorrect.

3. Final Answer:

   Using blocking assignment (=) inside sequential always block -> Option A

4. Quick Check:

   Use non-blocking (<=) in clocked blocks = C [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Ignoring missing default case (less critical)
• Confusing synchronous and asynchronous reset

5. You want to add a pedestrian crossing state to a traffic light FSM with states: Green (00), Yellow (01), Red (10), and Pedestrian Walk (11). Which state transition sequence correctly includes the pedestrian state after Red?

hard

A. Pedestrian Walk (11) -> Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11)

B. Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00)

C. Green (00) -> Yellow (01) -> Pedestrian Walk (11) -> Red (10) -> Green (00)

D. Green (00) -> Pedestrian Walk (11) -> Yellow (01) -> Red (10) -> Green (00)

Solution

1. Step 1: Understand safe traffic light sequence

   Normal sequence is Green -> Yellow -> Red, then pedestrian walk should come after Red for safety.

2. Step 2: Check options for correct order

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) correctly places Pedestrian Walk after Red, then cycles back to Green.

3. Final Answer:

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) -> Option B

4. Quick Check:

   Pedestrian after Red before Green = D [OK]

Hint: Pedestrian walk follows Red light for safety [OK]

Common Mistakes:

• Placing pedestrian walk before Yellow or Green
• Skipping pedestrian state in sequence
• Looping pedestrian state incorrectly