Traffic light controller FSM in Verilog - Mini Project: Build & Apply

Traffic Light Controller FSM

📖 Scenario: You are designing a simple traffic light controller for a crossroad. The traffic light cycles through green, yellow, and red lights in a fixed order to control the traffic flow safely.

🎯 Goal: Build a Verilog module that implements a traffic light controller using a finite state machine (FSM). The FSM will cycle through three states: green, yellow, and red. Each state will last for a fixed number of clock cycles.

📋 What You'll Learn

Create a Verilog module named traffic_light_controller with inputs clk and reset.

Define three states: GREEN, YELLOW, and RED using an enum.

Use a state register to hold the current state and a counter to count clock cycles for timing.

Cycle through the states in order: GREEN → YELLOW → RED → GREEN.

Output signals green_light, yellow_light, and red_light should be high only in their respective states.

💡 Why This Matters

🌍 Real World

Traffic light controllers are used in real intersections to manage vehicle and pedestrian traffic safely and efficiently.

💼 Career

Understanding FSM design in Verilog is essential for hardware engineers working on embedded systems, digital design, and FPGA programming.

1

Define the module and states

Create a Verilog module named traffic_light_controller with inputs clk and reset. Inside the module, define an enum type called state_t with three states: GREEN, YELLOW, and RED. Declare a variable state of type state_t to hold the current state.

Verilog

module traffic_light_controller(input clk, input reset);

// Define the states using enum
// Your code here

endmodule

Need a hint?

Use typedef enum logic [1:0] to define the states and declare a variable state of that type.

2

Add a counter for timing

Inside the traffic_light_controller module, declare a 4-bit register called counter to count clock cycles for timing the states. Initialize it to zero.

Verilog

module traffic_light_controller(input clk, input reset);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    // Declare a 4-bit counter register
    // Your code here

endmodule

Need a hint?

Use reg [3:0] counter = 4'd0; to declare and initialize the counter.

3

Implement the FSM state transitions

Add an always_ff block triggered on the rising edge of clk or when reset is high. Inside, if reset is high, set state to GREEN and counter to zero. Otherwise, increment counter. When counter reaches 4, reset it to zero and change state to the next state in the order: GREEN → YELLOW → RED → GREEN.

Verilog

module traffic_light_controller(input clk, input reset);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    reg [3:0] counter = 4'd0;

    // Add always_ff block for state transitions
    // Your code here

endmodule

Need a hint?

Use always_ff @(posedge clk or posedge reset) and a case statement to handle state changes.

4

Output the traffic light signals

Declare three output registers: green_light, yellow_light, and red_light. Use a combinational always_comb block to set these outputs high only when the state matches their color. Then, add output reg green_light, yellow_light, red_light to the module ports. Finally, print the current state name as a string using $display inside the always_ff block after state changes.

Verilog

module traffic_light_controller(input clk, input reset, output reg green_light, output reg yellow_light, output reg red_light);
    typedef enum logic [1:0] {GREEN, YELLOW, RED} state_t;
    state_t state;
    reg [3:0] counter = 4'd0;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= GREEN;
            counter <= 4'd0;
        end else begin
            if (counter == 4'd4) begin
                counter <= 4'd0;
                case (state)
                    GREEN: state <= YELLOW;
                    YELLOW: state <= RED;
                    RED: state <= GREEN;
                    default: state <= GREEN;
                endcase
            end else begin
                counter <= counter + 1;
            end
        end
    end

    // Add always_comb block to set output lights
    // Your code here

endmodule

Need a hint?

Use always_comb to set the outputs based on the current state. Use $display to print the state name after each change.