Traffic light controller FSM in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state register.

Verilog

reg [1:0] [1]; // 2-bit state register

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Astate

Btimer

Ccounter

Dflag

Attempts:

3 left

💡 Hint

Common Mistakes

Using unrelated names like counter or timer for the state register.

The state register is usually named state to hold the current FSM state.

2fill in blank

medium

Complete the code to define the state encoding for RED.

Verilog

localparam RED = 2'b[1];

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A11

B01

C10

D00

Attempts:

3 left

💡 Hint

Common Mistakes

Using 01 or 10 which represent other states.

The RED state is encoded as 2'b00 in this FSM.

3fill in blank

hard

Fix the error in the always block sensitivity list.

Verilog

always @([1]) begin
  if (reset) state <= RED;
  else state <= next_state;
end

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Areset

Bposedge clk

Cposedge clk or posedge reset

Dnegedge reset

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting reset or using wrong edge triggers.

The sensitivity list must include the clock and asynchronous reset signals with posedge.

4fill in blank

hard

Fill both blanks to complete the next state logic for RED to GREEN transition.

Verilog

always @(*) begin
  case(state)
    RED: if(timer [1] RED_TIME) next_state = [2]; else next_state = RED;
    default: next_state = RED;
  endcase
end

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A>=

B<

CGREEN

DYELLOW

Attempts:

3 left

💡 Hint

Common Mistakes

Using less than instead of greater or equal.

Setting next state incorrectly to YELLOW.

The FSM moves from RED to GREEN when the timer reaches or exceeds RED_TIME.

5fill in blank

hard

Fill all three blanks to complete the output logic for traffic lights.

Verilog

always @(*) begin
  case(state)
    RED: begin
      red_light = [1];
      yellow_light = [2];
      green_light = [3];
    end
    // other states omitted
  endcase
end

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A1'b1

B1'b0

Attempts:

3 left

💡 Hint

Common Mistakes

Turning on yellow or green lights in RED state.

In RED state, red_light is ON (1), yellow_light and green_light are OFF (0).

Practice

1. What is the main purpose of a traffic light controller FSM in Verilog?

easy

A. To detect traffic jams using sensors

B. To count the number of cars passing the intersection

C. To change traffic lights in a safe and timed sequence

D. To control the speed of vehicles on the road

Solution

1. Step 1: Understand FSM role in traffic lights

   A traffic light controller FSM manages the sequence of lights (red, yellow, green) safely and in timed order.

2. Step 2: Compare options to FSM purpose

   Only To change traffic lights in a safe and timed sequence describes changing lights in a safe and timed sequence, which is the FSM's job.

3. Final Answer:

   To change traffic lights in a safe and timed sequence -> Option C

4. Quick Check:

   FSM controls light sequence = A [OK]

Hint: FSM controls states and timing for lights [OK]

Common Mistakes:

• Confusing FSM with sensor or speed control
• Thinking FSM counts cars
• Assuming FSM controls vehicle speed

2. Which Verilog code snippet correctly declares the state variable for a traffic light FSM?

easy

A. logic state; // single bit logic variable

B. wire state; // single wire for state

C. integer state = 0; // integer state variable

D. reg [1:0] state; // 2-bit state variable

Solution

1. Step 1: Identify correct state variable type

   FSM states are stored in registers (reg) because they hold values across clock cycles.

2. Step 2: Check bit width for multiple states

   Traffic light FSM usually needs multiple bits (e.g., 2 bits) to represent states, so reg [1:0] is correct.

3. Final Answer:

   reg [1:0] state; // 2-bit state variable -> Option D

4. Quick Check:

   State needs reg and multiple bits = A [OK]

Hint: Use reg with enough bits for states [OK]

Common Mistakes:

• Using wire instead of reg for state
• Using single bit for multiple states
• Using integer without clocked assignment

3. Given this Verilog snippet for a traffic light FSM state transition:

always @(posedge clk) begin
  case(state)
    2'b00: state <= 2'b01;
    2'b01: state <= 2'b10;
    2'b10: state <= 2'b00;
    default: state <= 2'b00;
  endcase
end

What will be the sequence of states after 4 clock cycles starting from 2'b00?

medium

A. 00, 01, 10, 00

B. 00, 10, 01, 00

C. 00, 01, 00, 10

D. 00, 10, 10, 01

Solution

1. Step 1: Trace state transitions step-by-step

   Start at 00, next is 01, then 10, then back to 00 on each clock.

2. Step 2: List states for 4 cycles

   Cycle 1: 00, Cycle 2: 01, Cycle 3: 10, Cycle 4: 00.

3. Final Answer:

   00, 01, 10, 00 -> Option A

4. Quick Check:

   Follow case transitions = B [OK]

Hint: Follow case transitions in order [OK]

Common Mistakes:

• Mixing up state assignments order
• Forgetting default case resets state
• Assuming states skip steps

4. Identify the error in this Verilog FSM snippet for a traffic light controller:

always @(posedge clk) begin
  if (reset) state <= 2'b00;
  else
    case(state)
      2'b00: state = 2'b01;
      2'b01: state = 2'b10;
      2'b10: state = 2'b00;
    endcase
end

medium

A. Using blocking assignment (=) inside sequential always block

B. Missing default case in case statement

C. Reset condition should be asynchronous

D. State variable declared as wire instead of reg

Solution

1. Step 1: Check assignment types in clocked always block

   Inside always @(posedge clk), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify incorrect use of blocking assignment

   The code uses '=' (blocking) inside sequential logic, which is incorrect.

3. Final Answer:

   Using blocking assignment (=) inside sequential always block -> Option A

4. Quick Check:

   Use non-blocking (<=) in clocked blocks = C [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Ignoring missing default case (less critical)
• Confusing synchronous and asynchronous reset

5. You want to add a pedestrian crossing state to a traffic light FSM with states: Green (00), Yellow (01), Red (10), and Pedestrian Walk (11). Which state transition sequence correctly includes the pedestrian state after Red?

hard

A. Pedestrian Walk (11) -> Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11)

B. Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00)

C. Green (00) -> Yellow (01) -> Pedestrian Walk (11) -> Red (10) -> Green (00)

D. Green (00) -> Pedestrian Walk (11) -> Yellow (01) -> Red (10) -> Green (00)

Solution

1. Step 1: Understand safe traffic light sequence

   Normal sequence is Green -> Yellow -> Red, then pedestrian walk should come after Red for safety.

2. Step 2: Check options for correct order

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) correctly places Pedestrian Walk after Red, then cycles back to Green.

3. Final Answer:

   Green (00) -> Yellow (01) -> Red (10) -> Pedestrian Walk (11) -> Green (00) -> Option B

4. Quick Check:

   Pedestrian after Red before Green = D [OK]

Hint: Pedestrian walk follows Red light for safety [OK]

Common Mistakes:

• Placing pedestrian walk before Yellow or Green
• Skipping pedestrian state in sequence
• Looping pedestrian state incorrectly