0
0
Verilogprogramming~10 mins

Traffic light controller FSM in Verilog - Interactive Code Practice

Choose your learning style9 modes available
Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to declare the state register.

Verilog
reg [1:0] [1]; // 2-bit state register
Drag options to blanks, or click blank then click option'
Astate
Btimer
Ccounter
Dflag
Attempts:
3 left
💡 Hint
Common Mistakes
Using unrelated names like counter or timer for the state register.
2fill in blank
medium

Complete the code to define the state encoding for RED.

Verilog
localparam RED = 2'b[1];
Drag options to blanks, or click blank then click option'
A11
B01
C10
D00
Attempts:
3 left
💡 Hint
Common Mistakes
Using 01 or 10 which represent other states.
3fill in blank
hard

Fix the error in the always block sensitivity list.

Verilog
always @([1]) begin
  if (reset) state <= RED;
  else state <= next_state;
end
Drag options to blanks, or click blank then click option'
Areset
Bposedge clk
Cposedge clk or posedge reset
Dnegedge reset
Attempts:
3 left
💡 Hint
Common Mistakes
Omitting reset or using wrong edge triggers.
4fill in blank
hard

Fill both blanks to complete the next state logic for RED to GREEN transition.

Verilog
always @(*) begin
  case(state)
    RED: if(timer [1] RED_TIME) next_state = [2]; else next_state = RED;
    default: next_state = RED;
  endcase
end
Drag options to blanks, or click blank then click option'
A>=
B<
CGREEN
DYELLOW
Attempts:
3 left
💡 Hint
Common Mistakes
Using less than instead of greater or equal.
Setting next state incorrectly to YELLOW.
5fill in blank
hard

Fill all three blanks to complete the output logic for traffic lights.

Verilog
always @(*) begin
  case(state)
    RED: begin
      red_light = [1];
      yellow_light = [2];
      green_light = [3];
    end
    // other states omitted
  endcase
end
Drag options to blanks, or click blank then click option'
A1'b1
B1'b0
Attempts:
3 left
💡 Hint
Common Mistakes
Turning on yellow or green lights in RED state.