Practice - 5 Tasks
Answer the questions below
1fill in blank
easyComplete the code to declare the state register.
Verilog
reg [1:0] [1]; // 2-bit state register
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Attempts:
3 left
💡 Hint
Common Mistakes
Using unrelated names like counter or timer for the state register.
✗ Incorrect
The state register is usually named state to hold the current FSM state.
2fill in blank
mediumComplete the code to define the state encoding for RED.
Verilog
localparam RED = 2'b[1];
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Attempts:
3 left
💡 Hint
Common Mistakes
Using 01 or 10 which represent other states.
✗ Incorrect
The RED state is encoded as 2'b00 in this FSM.
3fill in blank
hardFix the error in the always block sensitivity list.
Verilog
always @([1]) begin if (reset) state <= RED; else state <= next_state; end
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Attempts:
3 left
💡 Hint
Common Mistakes
Omitting reset or using wrong edge triggers.
✗ Incorrect
The sensitivity list must include the clock and asynchronous reset signals with posedge.
4fill in blank
hardFill both blanks to complete the next state logic for RED to GREEN transition.
Verilog
always @(*) begin
case(state)
RED: if(timer [1] RED_TIME) next_state = [2]; else next_state = RED;
default: next_state = RED;
endcase
end Drag options to blanks, or click blank then click option'
Attempts:
3 left
💡 Hint
Common Mistakes
Using less than instead of greater or equal.
Setting next state incorrectly to YELLOW.
✗ Incorrect
The FSM moves from RED to GREEN when the timer reaches or exceeds RED_TIME.
5fill in blank
hardFill all three blanks to complete the output logic for traffic lights.
Verilog
always @(*) begin
case(state)
RED: begin
red_light = [1];
yellow_light = [2];
green_light = [3];
end
// other states omitted
endcase
end Drag options to blanks, or click blank then click option'
Attempts:
3 left
💡 Hint
Common Mistakes
Turning on yellow or green lights in RED state.
✗ Incorrect
In RED state, red_light is ON (1), yellow_light and green_light are OFF (0).