Traffic light controller FSM in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple traffic light FSM

What is the output of the traffic light signals after the first clock cycle in this FSM code?

Verilog

module traffic_light_fsm(input clk, input reset, output reg [1:0] light);
  typedef enum reg [1:0] {RED=2'b00, GREEN=2'b01, YELLOW=2'b10} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= RED;
    else state <= next_state;
  end

  always @(*) begin
    case(state)
      RED: next_state = GREEN;
      GREEN: next_state = YELLOW;
      YELLOW: next_state = RED;
      default: next_state = RED;
    endcase
  end

  always @(*) begin
    light = state;
  end
endmodule

A light = 2'b00 (RED)

B light = 2'b01 (GREEN)

C light = 2'b10 (YELLOW)

D light = 2'b11 (undefined)

💡 Hint

Remember the FSM starts at RED state on reset.

On reset, the FSM state is set to RED (2'b00). The output light reflects the current state before the clock edge updates it.

🧠 Conceptual

intermediate

Understanding state transitions in traffic light FSM

In the traffic light FSM, what is the next state after the GREEN state?

A RED

B YELLOW

C GREEN

D OFF

💡 Hint

Check the case statement for the GREEN state.

The FSM transitions from GREEN to YELLOW as per the case statement in the next_state logic.

🔧 Debug

advanced

Identify the error in this traffic light FSM code

What error will this Verilog code produce when simulating the traffic light FSM?

Verilog

module traffic_light_fsm(input clk, input reset, output reg [1:0] light);
  typedef enum reg [1:0] {RED=2'b00, GREEN=2'b01, YELLOW=2'b10} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= RED;
    else state <= next_state;
  end

  always @(*) begin
    case(state)
      RED: next_state = GREEN;
      GREEN: next_state = YELLOW;
      YELLOW: next_state = RED;
      default: next_state = RED;
    endcase
  end

  always @(*) begin
    light = next_state;
  end
endmodule

A light output is always zero

B Syntax error: missing semicolon after typedef

C Runtime error: state never updates

D light output shows the next state, not current state

💡 Hint

Check which state variable is assigned to light output.

The light output should reflect the current state, but here it shows next_state, causing output to change early.

📝 Syntax

advanced

Find the syntax error in this traffic light FSM snippet

Which option correctly fixes the syntax error in this code snippet?

Verilog

always @(posedge clk or posedge reset) begin
  if reset
    state <= RED;
  else
    state <= next_state;
end

A if (reset) { state <= RED; }

B if reset: state <= RED;

C if (reset) state <= RED;

D if reset then state <= RED;

💡 Hint

Verilog requires parentheses around conditions in if statements.

Verilog syntax for if requires parentheses around the condition without colons or braces.

🚀 Application

expert

Number of states in a traffic light FSM with pedestrian crossing

A traffic light FSM has states: RED, GREEN, YELLOW, and a PEDESTRIAN_WAIT state. How many unique states does this FSM have?

A 4

B 6

C 3

D 5

💡 Hint

Count all named states including pedestrian wait.

The FSM has four unique states: RED, GREEN, YELLOW, and PEDESTRIAN_WAIT.