Traffic light controller FSM in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Finite State Machine (FSM) in the context of a traffic light controller?

An FSM is a model that controls the traffic light by moving through a set of defined states (like green, yellow, red) in a specific order based on timing or events.

beginner

In Verilog, how do you represent states for a traffic light controller FSM?

States are usually represented using parameters or localparams with unique binary values, for example: parameter GREEN = 2'b00, YELLOW = 2'b01, RED = 2'b10.

beginner

What is the role of the clock signal in a traffic light FSM implemented in Verilog?

The clock signal triggers state changes at regular intervals, ensuring the traffic light changes colors in a timed sequence.

beginner

Why do we use a reset signal in a traffic light controller FSM?

The reset signal initializes the FSM to a known starting state (usually RED) when the system powers on or needs to restart safely.

intermediate

How does the traffic light controller FSM ensure safe transitions between states?

It uses a defined sequence and timing for states, for example, green to yellow to red, preventing conflicting signals and ensuring safety.

What does FSM stand for in a traffic light controller?

A Frequency Signal Monitor

B Fast Signal Module

C Finite State Machine

D Flow State Model

FSM means Finite State Machine, a model used to control sequences like traffic lights.

Which Verilog construct is commonly used to define states in a traffic light FSM?

A parameter or localparam

B wire

C reg

D module

Parameters or localparams define constant state values for clarity and easy state management.

What triggers the state transitions in a traffic light FSM?

A Clock signal

B Reset signal

C Input button

D Power supply

The clock signal controls when the FSM moves from one state to the next.

Why is a reset signal important in a traffic light FSM?

A To change the light colors randomly

B To initialize the FSM to a safe starting state

C To speed up the clock

D To turn off the traffic lights

Reset sets the FSM to a known safe state, usually red, when starting or recovering.

What is the correct sequence of states in a simple traffic light FSM?

A Green → Red → Yellow

B Red → Green → Yellow

C Yellow → Red → Green

D Green → Yellow → Red

The safe and common sequence is green, then yellow, then red.

Explain how a traffic light controller FSM works in Verilog, including states, clock, and reset.

Think about how the traffic light changes colors step by step.

Describe why timing and state order are important in a traffic light FSM.

Consider what happens if lights change too fast or in wrong order.