T flip-flop behavior in Verilog - Step-by-Step Execution

Concept Flow - T flip-flop behavior

Start

↓

Clock Edge?

No→Wait

Yes↓

Check T Input

↓

T=0

↓

Q=Q

↓

Output Q

↓

Wait for next clock

On each clock edge, if T is 0, output Q stays the same; if T is 1, output Q toggles.

Execution Sample

Verilog

always @(posedge clk) begin
  if (T == 1) Q <= ~Q;
  else Q <= Q;
end

This code toggles Q on clock edge if T is 1, else Q stays the same.

Execution Table

Step	Clock Edge	T Input	Previous Q	Action	New Q
1	Yes	0	0	Q stays the same	0
2	Yes	1	0	Q toggles	1
3	Yes	1	1	Q toggles	0
4	Yes	0	0	Q stays the same	0
5	No	1	0	No clock edge, no change	0

💡 No clock edge at step 5, so Q does not change and execution waits for next clock.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
Q	0	0	1	0	0	0
T	0	0	1	1	0	1
Clock Edge	N/A	Yes	Yes	Yes	Yes	No

Key Moments - 3 Insights

Why does Q not change when T is 0 at a clock edge?

Because when T=0, the flip-flop holds its previous state, as shown in execution_table rows 1 and 4 where Q remains unchanged.

What happens to Q when T=1 at a clock edge?

Q toggles its value (0 to 1 or 1 to 0), as seen in execution_table rows 2 and 3.

Why is there no change in Q at step 5 despite T=1?

Because there is no clock edge at step 5, so the flip-flop does not update Q, as indicated in the exit_note and execution_table row 5.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of Q after step 3?

A Undefined

B 0

C 1

D Same as T

💡 Hint

Check the 'New Q' column at step 3 in the execution_table.

At which step does the condition 'T=1' cause Q to toggle from 0 to 1?

A Step 4

B Step 1

C Step 2

D Step 5

💡 Hint

Look at the 'T Input' and 'Action' columns in execution_table rows.

If the clock edge was missing at step 2, what would happen to Q?

A Q would stay the same

B Q would toggle anyway

C Q would reset to 0

D Q would become equal to T

💡 Hint

Refer to step 5 in execution_table where no clock edge means no change in Q.

Concept Snapshot

T Flip-Flop Behavior in Verilog:
- On rising clock edge, check T input.
- If T=0, Q holds its value.
- If T=1, Q toggles (0->1 or 1->0).
- No clock edge means no change.
- Code: always @(posedge clk) if (T) Q <= ~Q; else Q <= Q;

Full Transcript

This visual execution shows how a T flip-flop works in Verilog. On each rising clock edge, the flip-flop checks the T input. If T is 0, the output Q stays the same. If T is 1, Q toggles its value from 0 to 1 or from 1 to 0. When there is no clock edge, Q does not change regardless of T. The execution table traces Q and T values step-by-step, showing how Q updates or holds. Key moments clarify why Q changes or stays the same depending on T and clock edges. The quiz tests understanding of Q's value changes at specific steps. This helps beginners see the flip-flop's behavior clearly.