T flip-flop behavior in Verilog - Step-by-Step Execution

Concept Flow - T flip-flop behavior

Start

↓

Clock Edge?

No→Wait

Yes↓

Check T Input

↓

T=0

↓

Q=Q

↓

Output Q

↓

Wait for next clock

On each clock edge, if T is 0, output Q stays the same; if T is 1, output Q toggles.

Execution Sample

Verilog

always @(posedge clk) begin
  if (T == 1) Q <= ~Q;
  else Q <= Q;
end

This code toggles Q on clock edge if T is 1, else Q stays the same.

Execution Table

Step	Clock Edge	T Input	Previous Q	Action	New Q
1	Yes	0	0	Q stays the same	0
2	Yes	1	0	Q toggles	1
3	Yes	1	1	Q toggles	0
4	Yes	0	0	Q stays the same	0
5	No	1	0	No clock edge, no change	0

💡 No clock edge at step 5, so Q does not change and execution waits for next clock.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
Q	0	0	1	0	0	0
T	0	0	1	1	0	1
Clock Edge	N/A	Yes	Yes	Yes	Yes	No

Key Moments - 3 Insights

Why does Q not change when T is 0 at a clock edge?

Because when T=0, the flip-flop holds its previous state, as shown in execution_table rows 1 and 4 where Q remains unchanged.

What happens to Q when T=1 at a clock edge?

Q toggles its value (0 to 1 or 1 to 0), as seen in execution_table rows 2 and 3.

Why is there no change in Q at step 5 despite T=1?

Because there is no clock edge at step 5, so the flip-flop does not update Q, as indicated in the exit_note and execution_table row 5.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of Q after step 3?

A Undefined

B 0

C 1

D Same as T

💡 Hint

Check the 'New Q' column at step 3 in the execution_table.

At which step does the condition 'T=1' cause Q to toggle from 0 to 1?

A Step 4

B Step 1

C Step 2

D Step 5

💡 Hint

Look at the 'T Input' and 'Action' columns in execution_table rows.

If the clock edge was missing at step 2, what would happen to Q?

A Q would stay the same

B Q would toggle anyway

C Q would reset to 0

D Q would become equal to T

💡 Hint

Refer to step 5 in execution_table where no clock edge means no change in Q.

Concept Snapshot

T Flip-Flop Behavior in Verilog:
- On rising clock edge, check T input.
- If T=0, Q holds its value.
- If T=1, Q toggles (0->1 or 1->0).
- No clock edge means no change.
- Code: always @(posedge clk) if (T) Q <= ~Q; else Q <= Q;

Full Transcript

This visual execution shows how a T flip-flop works in Verilog. On each rising clock edge, the flip-flop checks the T input. If T is 0, the output Q stays the same. If T is 1, Q toggles its value from 0 to 1 or from 1 to 0. When there is no clock edge, Q does not change regardless of T. The execution table traces Q and T values step-by-step, showing how Q updates or holds. Key moments clarify why Q changes or stays the same depending on T and clock edges. The quiz tests understanding of Q's value changes at specific steps. This helps beginners see the flip-flop's behavior clearly.

Practice

1. What happens to the output Q of a T flip-flop when the input T is 1 at the rising edge of the clock?

easy

A. The output Q toggles (changes from 0 to 1 or 1 to 0).

B. The output Q resets to 0.

C. The output Q stays the same.

D. The output Q sets to 1.

Solution

1. Step 1: Understand T flip-flop behavior

   A T flip-flop toggles its output Q when T is 1 at the clock's rising edge.

2. Step 2: Apply the toggle rule

   Since T is 1, Q changes from 0 to 1 or 1 to 0.

3. Final Answer:

   The output Q toggles (changes from 0 to 1 or 1 to 0). -> Option A

4. Quick Check:

   T=1 causes toggle = A [OK]

Hint: Remember: T=1 toggles output Q on clock edge [OK]

Common Mistakes:

• Thinking output resets when T=1
• Assuming output stays the same always
• Confusing T flip-flop with D flip-flop

2. Which of the following is the correct Verilog sensitivity list for a T flip-flop with asynchronous reset rst and clock clk?

easy

A. always @(posedge clk or posedge rst)

B. always @(negedge clk or negedge rst)

C. always @(clk or rst)

D. always @(posedge rst or negedge clk)

Solution

1. Step 1: Identify asynchronous reset and clock edge

   Asynchronous reset triggers on positive edge of rst, clock triggers on positive edge of clk.

2. Step 2: Write sensitivity list accordingly

   Sensitivity list must include posedge clk and posedge rst for asynchronous reset.

3. Final Answer:

   always @(posedge clk or posedge rst) -> Option A

4. Quick Check:

   Async reset and posedge clock = A [OK]

Hint: Async reset uses posedge or negedge in sensitivity list [OK]

Common Mistakes:

• Using level-sensitive instead of edge-sensitive triggers
• Mixing posedge and negedge incorrectly
• Omitting reset from sensitivity list

3. Given the following Verilog code for a T flip-flop, what is the value of Q after two rising edges of clk if T=1 and rst=0 initially?

module t_ff(input clk, rst, T, output reg Q);
  always @(posedge clk or posedge rst) begin
    if (rst) Q <= 0;
    else if (T) Q <= ~Q;
  end
endmodule

medium

A. Q toggles once, so final Q = ~initial Q

B. Q toggles twice, so final Q = initial Q

C. Q resets to 0 after two clocks

D. Q remains unchanged

Solution

1. Step 1: Analyze behavior on each clock edge

   At each rising edge, since T=1 and rst=0, Q toggles.

2. Step 2: Calculate after two toggles

   Two toggles mean Q changes twice, returning to its initial value.

3. Final Answer:

   Q toggles twice, so final Q = initial Q -> Option B

4. Quick Check:

   Two toggles return Q to initial = B [OK]

Hint: Even toggles return Q to start value [OK]

Common Mistakes:

• Assuming Q toggles only once after two clocks
• Forgetting reset is zero so no reset occurs
• Confusing toggle with set or reset

4. Identify the error in this Verilog T flip-flop code snippet:

always @(posedge clk or posedge rst) begin
  if (rst == 1'b1)
    Q = 0;
  else if (T == 1'b1)
    Q = ~Q;
end

medium

A. No initial value assigned to Q

B. Missing sensitivity to negedge clk

C. Using blocking assignments = instead of non-blocking <= inside always block

D. Incorrect reset condition syntax

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic inside always @(posedge clk ...) must use non-blocking assignments <=.

2. Step 2: Identify the error

   The code uses blocking assignments =, which can cause simulation mismatches.

3. Final Answer:

   Using blocking assignments = instead of non-blocking <= inside always block -> Option C

4. Quick Check:

   Sequential logic needs non-blocking <= = D [OK]

Hint: Use <= for sequential logic inside always @(posedge clk) [OK]

Common Mistakes:

• Using blocking = instead of non-blocking <=
• Adding negedge clk unnecessarily
• Miswriting reset condition syntax

5. You want to design a frequency divider by 4 using T flip-flops in Verilog. How many T flip-flops connected in series are needed, and what should be the input T for each flip-flop to achieve this?

hard

A. 1 T flip-flop with T toggling every 4 clock cycles

B. 4 T flip-flops, each with T=0 to hold state

C. 3 T flip-flops, each with T=1 to toggle on every clock edge

D. 2 T flip-flops, each with T=1 to toggle on every clock edge

Solution

1. Step 1: Calculate number of flip-flops for divide by 4

   Divide by 4 requires 2^n = 4, so n = 2 flip-flops. A chain of 2 toggling flip-flops achieves frequency divide by 4.

2. Step 2: Consider toggle input for frequency division

   Each T flip-flop must toggle (T=1) on its clock input. The first flip-flop toggles on main clock, the next toggles on previous flip-flop output.

3. Step 3: Confirm the configuration

   2 T flip-flops chained with T=1 for each achieves divide-by-4.

4. Final Answer:

   2 T flip-flops, each with T=1 to toggle on every clock edge -> Option D

5. Quick Check:

   Divide by 4 needs 2 toggling T flip-flops = C [OK]

Hint: Divide by 2^n needs n T flip-flops toggling [OK]

Common Mistakes:

• Using wrong number of flip-flops for division
• Setting T=0 so flip-flops don't toggle
• Confusing divide by 4 with divide by 8