T flip-flop behavior in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the main function of a T flip-flop?

A T flip-flop toggles its output on each clock pulse when the T input is high (1). If T is low (0), the output remains the same.

beginner

Explain the behavior of a T flip-flop when T = 0.

When T = 0, the T flip-flop holds its current state and does not change output on the clock edge.

intermediate

Write the Verilog sensitivity list for a T flip-flop triggered on the positive edge of the clock.

The sensitivity list is: always @(posedge clk) begin ... end which means the block runs on the rising edge of the clock signal.

beginner

What happens to the output Q of a T flip-flop if T = 1 and a clock pulse occurs?

The output Q toggles its value: if Q was 0, it becomes 1; if Q was 1, it becomes 0.

intermediate

Show a simple Verilog code snippet for a T flip-flop behavior.

always @(posedge clk) begin if (T) Q <= ~Q; // Toggle output else Q <= Q; // Hold output end

What does a T flip-flop do when T = 1 at the clock's rising edge?

A It holds the current output Q

B It resets the output Q to 0

C It sets the output Q to 1

D It toggles the output Q

When T = 1, the T flip-flop toggles its output Q on the clock's rising edge.

Which Verilog keyword is used to describe behavior on a clock edge?

A always @(posedge clk)

B if (clk)

C while (clk)

D case (clk)

The 'always @(posedge clk)' block runs code on the positive (rising) edge of the clock.

If T = 0, what happens to the output Q of a T flip-flop at the clock edge?

A Q toggles

B Q holds its previous value

C Q resets to 0

D Q sets to 1

When T = 0, the T flip-flop holds its current output value.

What is the output Q after two clock pulses if T = 1 and initial Q = 0?

A 0

B 1

C Toggles twice, so back to 0

D Undefined

With T = 1, Q toggles each clock pulse: 0 -> 1 (first pulse), 1 -> 0 (second pulse).

Which statement best describes a T flip-flop?

A It stores data and toggles output based on T input

B It only resets output

C It only sets output

D It is asynchronous

A T flip-flop stores data and toggles output Q when T input is high on clock edge.

Describe how a T flip-flop behaves with respect to its T input and clock signal.

Think about when the output changes and when it stays the same.

Write a simple Verilog always block that models a T flip-flop triggered on the positive edge of the clock.

Use if condition inside the always block to check T input.

Practice

1. What happens to the output Q of a T flip-flop when the input T is 1 at the rising edge of the clock?

easy

A. The output Q toggles (changes from 0 to 1 or 1 to 0).

B. The output Q resets to 0.

C. The output Q stays the same.

D. The output Q sets to 1.

Solution

1. Step 1: Understand T flip-flop behavior

   A T flip-flop toggles its output Q when T is 1 at the clock's rising edge.

2. Step 2: Apply the toggle rule

   Since T is 1, Q changes from 0 to 1 or 1 to 0.

3. Final Answer:

   The output Q toggles (changes from 0 to 1 or 1 to 0). -> Option A

4. Quick Check:

   T=1 causes toggle = A [OK]

Hint: Remember: T=1 toggles output Q on clock edge [OK]

Common Mistakes:

• Thinking output resets when T=1
• Assuming output stays the same always
• Confusing T flip-flop with D flip-flop

2. Which of the following is the correct Verilog sensitivity list for a T flip-flop with asynchronous reset rst and clock clk?

easy

A. always @(posedge clk or posedge rst)

B. always @(negedge clk or negedge rst)

C. always @(clk or rst)

D. always @(posedge rst or negedge clk)

Solution

1. Step 1: Identify asynchronous reset and clock edge

   Asynchronous reset triggers on positive edge of rst, clock triggers on positive edge of clk.

2. Step 2: Write sensitivity list accordingly

   Sensitivity list must include posedge clk and posedge rst for asynchronous reset.

3. Final Answer:

   always @(posedge clk or posedge rst) -> Option A

4. Quick Check:

   Async reset and posedge clock = A [OK]

Hint: Async reset uses posedge or negedge in sensitivity list [OK]

Common Mistakes:

• Using level-sensitive instead of edge-sensitive triggers
• Mixing posedge and negedge incorrectly
• Omitting reset from sensitivity list

3. Given the following Verilog code for a T flip-flop, what is the value of Q after two rising edges of clk if T=1 and rst=0 initially?

module t_ff(input clk, rst, T, output reg Q);
  always @(posedge clk or posedge rst) begin
    if (rst) Q <= 0;
    else if (T) Q <= ~Q;
  end
endmodule

medium

A. Q toggles once, so final Q = ~initial Q

B. Q toggles twice, so final Q = initial Q

C. Q resets to 0 after two clocks

D. Q remains unchanged

Solution

1. Step 1: Analyze behavior on each clock edge

   At each rising edge, since T=1 and rst=0, Q toggles.

2. Step 2: Calculate after two toggles

   Two toggles mean Q changes twice, returning to its initial value.

3. Final Answer:

   Q toggles twice, so final Q = initial Q -> Option B

4. Quick Check:

   Two toggles return Q to initial = B [OK]

Hint: Even toggles return Q to start value [OK]

Common Mistakes:

• Assuming Q toggles only once after two clocks
• Forgetting reset is zero so no reset occurs
• Confusing toggle with set or reset

4. Identify the error in this Verilog T flip-flop code snippet:

always @(posedge clk or posedge rst) begin
  if (rst == 1'b1)
    Q = 0;
  else if (T == 1'b1)
    Q = ~Q;
end

medium

A. No initial value assigned to Q

B. Missing sensitivity to negedge clk

C. Using blocking assignments = instead of non-blocking <= inside always block

D. Incorrect reset condition syntax

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic inside always @(posedge clk ...) must use non-blocking assignments <=.

2. Step 2: Identify the error

   The code uses blocking assignments =, which can cause simulation mismatches.

3. Final Answer:

   Using blocking assignments = instead of non-blocking <= inside always block -> Option C

4. Quick Check:

   Sequential logic needs non-blocking <= = D [OK]

Hint: Use <= for sequential logic inside always @(posedge clk) [OK]

Common Mistakes:

• Using blocking = instead of non-blocking <=
• Adding negedge clk unnecessarily
• Miswriting reset condition syntax

5. You want to design a frequency divider by 4 using T flip-flops in Verilog. How many T flip-flops connected in series are needed, and what should be the input T for each flip-flop to achieve this?

hard

A. 1 T flip-flop with T toggling every 4 clock cycles

B. 4 T flip-flops, each with T=0 to hold state

C. 3 T flip-flops, each with T=1 to toggle on every clock edge

D. 2 T flip-flops, each with T=1 to toggle on every clock edge

Solution

1. Step 1: Calculate number of flip-flops for divide by 4

   Divide by 4 requires 2^n = 4, so n = 2 flip-flops. A chain of 2 toggling flip-flops achieves frequency divide by 4.

2. Step 2: Consider toggle input for frequency division

   Each T flip-flop must toggle (T=1) on its clock input. The first flip-flop toggles on main clock, the next toggles on previous flip-flop output.

3. Step 3: Confirm the configuration

   2 T flip-flops chained with T=1 for each achieves divide-by-4.

4. Final Answer:

   2 T flip-flops, each with T=1 to toggle on every clock edge -> Option D

5. Quick Check:

   Divide by 4 needs 2 toggling T flip-flops = C [OK]

Hint: Divide by 2^n needs n T flip-flops toggling [OK]

Common Mistakes:

• Using wrong number of flip-flops for division
• Setting T=0 so flip-flops don't toggle
• Confusing divide by 4 with divide by 8