T flip-flop behavior in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the main function of a T flip-flop?

A T flip-flop toggles its output on each clock pulse when the T input is high (1). If T is low (0), the output remains the same.

beginner

Explain the behavior of a T flip-flop when T = 0.

When T = 0, the T flip-flop holds its current state and does not change output on the clock edge.

intermediate

Write the Verilog sensitivity list for a T flip-flop triggered on the positive edge of the clock.

The sensitivity list is: always @(posedge clk) begin ... end which means the block runs on the rising edge of the clock signal.

beginner

What happens to the output Q of a T flip-flop if T = 1 and a clock pulse occurs?

The output Q toggles its value: if Q was 0, it becomes 1; if Q was 1, it becomes 0.

intermediate

Show a simple Verilog code snippet for a T flip-flop behavior.

always @(posedge clk) begin if (T) Q <= ~Q; // Toggle output else Q <= Q; // Hold output end

What does a T flip-flop do when T = 1 at the clock's rising edge?

A It holds the current output Q

B It resets the output Q to 0

C It sets the output Q to 1

D It toggles the output Q

When T = 1, the T flip-flop toggles its output Q on the clock's rising edge.

Which Verilog keyword is used to describe behavior on a clock edge?

A always @(posedge clk)

B if (clk)

C while (clk)

D case (clk)

The 'always @(posedge clk)' block runs code on the positive (rising) edge of the clock.

If T = 0, what happens to the output Q of a T flip-flop at the clock edge?

A Q toggles

B Q holds its previous value

C Q resets to 0

D Q sets to 1

When T = 0, the T flip-flop holds its current output value.

What is the output Q after two clock pulses if T = 1 and initial Q = 0?

A 0

B 1

C Toggles twice, so back to 0

D Undefined

With T = 1, Q toggles each clock pulse: 0 -> 1 (first pulse), 1 -> 0 (second pulse).

Which statement best describes a T flip-flop?

A It stores data and toggles output based on T input

B It only resets output

C It only sets output

D It is asynchronous

A T flip-flop stores data and toggles output Q when T input is high on clock edge.

Describe how a T flip-flop behaves with respect to its T input and clock signal.

Think about when the output changes and when it stays the same.

Write a simple Verilog always block that models a T flip-flop triggered on the positive edge of the clock.

Use if condition inside the always block to check T input.