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Verilogprogramming~20 mins

T flip-flop behavior in Verilog - Practice Problems & Coding Challenges

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Challenge - 5 Problems
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T Flip-Flop Mastery
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❓ Predict Output
intermediate
2:00remaining
Output of T Flip-Flop with Toggle Input
What is the output q after 4 positive clock edges if t = 1 and initial q = 0?
Verilog
module t_ff(input clk, input t, output reg q);
  always @(posedge clk) begin
    if (t)
      q <= ~q;
  end
endmodule

// Initial q = 0, t = 1, 4 clock cycles
Aq toggles randomly
Bq = 1
Cq = 0 after 2 cycles, then 1 after 4 cycles
Dq = 0
Attempts:
2 left
💡 Hint
Remember that T flip-flop toggles output on each clock edge when T=1.
❓ Predict Output
intermediate
2:00remaining
Behavior with T=0 Input
What will be the output q after 3 positive clock edges if t = 0 and initial q = 1?
Verilog
module t_ff(input clk, input t, output reg q);
  always @(posedge clk) begin
    if (t)
      q <= ~q;
  end
endmodule

// Initial q = 1, t = 0, 3 clock cycles
Aq = 0
Bq toggles every clock
Cq = 1
Dq becomes undefined
Attempts:
2 left
💡 Hint
When T=0, the flip-flop should hold its value.
🔧 Debug
advanced
2:00remaining
Identify the Syntax Error in T Flip-Flop Code
Which option contains a syntax error preventing the T flip-flop from compiling?
Verilog
always @(posedge clk) begin
  if t == 1
    q <= ~q;
end
Aif t == 1 q <= ~q;
Bif (t == 1) begin q <= ~q; end
Cif (t == 1) q <= ~q;
Dif (t) q <= ~q;
Attempts:
2 left
💡 Hint
Check the syntax for if statements in Verilog.
🧠 Conceptual
advanced
2:00remaining
Effect of Asynchronous Reset on T Flip-Flop
What is the effect of adding an asynchronous active-low reset rst_n to a T flip-flop?
AFlip-flop output resets to 1 on clock edge when <code>rst_n</code> is low
BFlip-flop output resets to 0 immediately when <code>rst_n</code> is low, regardless of clock
CFlip-flop toggles output only when <code>rst_n</code> is low
DFlip-flop ignores <code>rst_n</code> and toggles normally
Attempts:
2 left
💡 Hint
Asynchronous reset acts immediately, not waiting for clock.
❓ Predict Output
expert
3:00remaining
Output Sequence of T Flip-Flop with Mixed T Input
Given initial q = 0, and t input sequence over 5 clock cycles: [1, 0, 1, 1, 0], what is the output q after the 5th clock edge?
Verilog
module t_ff(input clk, input t, output reg q);
  always @(posedge clk) begin
    if (t)
      q <= ~q;
  end
endmodule

// Initial q=0, t sequence: 1,0,1,1,0
Aq = 1
Bq = 0
Cq = 1 after 3 cycles, then 0 after 5 cycles
Dq toggles every cycle regardless of t
Attempts:
2 left
💡 Hint
Toggle q only when t=1 at clock edge.