T flip-flop behavior in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the T input in the module.

Verilog

module t_flip_flop(clk, t, q);
  input clk, [1];
  output reg q;
  always @(posedge clk) begin
    if (t)
      q <= ~q;
  end
endmodule

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Aq

Bt

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'q' as input instead of 't'.

Forgetting to declare 't' as input.

The T input must be declared as an input to control toggling.

2fill in blank

medium

Complete the code to toggle q when t is high on clock edge.

Verilog

always @(posedge clk) begin
  if ([1])
    q <= ~q;
end

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Aq

Bclk

Ct

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' inside the if condition.

Using 'q' instead of 't' in the condition.

The flip-flop toggles q only when t is high at the clock's rising edge.

3fill in blank

hard

Fix the error in the sensitivity list to trigger on clock's rising edge.

Verilog

always @([1]) begin
  if (t)
    q <= ~q;
end

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Aposedge clk

Bnegedge clk

Cclk

Dt

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge clk' instead of 'posedge clk'.

Using just 'clk' without edge specification.

The flip-flop should trigger on the positive edge of the clock.

4fill in blank

hard

Fill both blanks to complete the module header and output declaration.

Verilog

module t_flip_flop([1], [2], q);
  input clk, t;
  output reg q;
endmodule

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Aclk

Bt

Cq

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Putting output 'q' before inputs.

Missing 't' in the header.

The module header lists inputs clk and t before output q.

5fill in blank

hard

Fill all three blanks to complete the always block for T flip-flop behavior.

Verilog

always @([1]) begin
  if ([2])
    q <= [3];
end

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Aposedge clk

Bt

C~q

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using negedge clk instead of posedge clk.

Assigning q instead of ~q to toggle.

The always block triggers on posedge clk, toggles q if t is high by assigning ~q.