T flip-flop behavior in Verilog - Mini Project: Build & Apply

T Flip-Flop Behavior

📖 Scenario: You are designing a simple digital circuit that uses a T flip-flop to toggle an output signal. This is a common component in counters and memory elements.

🎯 Goal: Build a Verilog module that models the behavior of a T flip-flop. The flip-flop should toggle its output on every rising edge of the clock when the T input is high.

📋 What You'll Learn

Create a Verilog module named t_flip_flop with inputs clk and t, and output q.

Add a register q to hold the flip-flop state.

Use an always block triggered on the rising edge of clk.

Inside the always block, toggle q if t is 1; otherwise, keep q unchanged.

Print the value of q after toggling in the testbench.

💡 Why This Matters

🌍 Real World

T flip-flops are used in digital circuits for toggling signals, building counters, and memory elements.

💼 Career

Understanding flip-flop behavior is essential for hardware design engineers and anyone working with digital logic and FPGA programming.

1

Create the T flip-flop module and declare inputs and output

Write a Verilog module named t_flip_flop with inputs clk and t, and an output register q.

Verilog

module t_flip_flop(input clk, input t, output reg q);
// Your code here
endmodule

Need a hint?

Start by declaring the module and its ports exactly as specified.

2

Add the always block triggered on the rising edge of clk

Inside the t_flip_flop module, add an always block triggered on the rising edge of clk.

Verilog

module t_flip_flop(input clk, input t, output reg q);
    always @(posedge clk) begin
        // Your code here
    end
endmodule

Need a hint?

Use always @(posedge clk) to detect rising clock edges.

3

Implement toggling behavior inside the always block

Inside the always block, write code to toggle q when t is 1, otherwise keep q unchanged.

Verilog

module t_flip_flop(input clk, input t, output reg q);
    always @(posedge clk) begin
        if (t == 1) begin
            // Your code here
        end
    end
endmodule

Need a hint?

Use q <= ~q; to toggle the output.

4

Create a testbench to simulate and print the output

Write a testbench module named testbench that instantiates t_flip_flop, applies clock and T input signals, and prints the value of q after each clock rising edge.

Verilog

module testbench;
    reg clk = 0;
    reg t = 0;
    wire q;

    t_flip_flop uut(clk, t, q);

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        // Your code here
    end
endmodule

Need a hint?

Toggle the clock every 5 time units. Set t to 1 to enable toggling. Use $display inside always @(posedge clk) to print q.