Single-port RAM design in Verilog - Step-by-Step Execution

Concept Flow - Single-port RAM design

Start

↓

Check write_enable?

No→Read data at address

|Yes↓

Write data at address

↓

Output data

↓

End

The RAM checks if write is enabled; if yes, it writes data to the address, else it reads data from the address and outputs it.

Execution Sample

Verilog

module single_port_ram(
  input clk,
  input we,
  input [3:0] addr,
  input [7:0] din,
  output reg [7:0] dout
);
  reg [7:0] ram [0:15];
  always @(posedge clk) begin
    if (we) begin
      ram[addr] <= din;
      dout <= din;
    end else begin
      dout <= ram[addr];
    end
  end
endmodule

This code defines a 16x8-bit single-port RAM with synchronous write and read on clock edge.

Execution Table

Step	clk edge	write_enable (we)	addr	din	Action	dout (output)
1	rising	1	4	10101010	Write 10101010 at addr 4; Read addr 4	10101010
2	rising	0	4	XXXXXXXX	No write; Read addr 4	10101010
3	rising	1	2	11110000	Write 11110000 at addr 2; Read addr 2	11110000
4	rising	0	2	XXXXXXXX	No write; Read addr 2	11110000
5	rising	0	4	XXXXXXXX	No write; Read addr 4	10101010

💡 Simulation ends after 5 clock cycles demonstrating write and read operations.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
ram[4]	undefined	10101010	10101010	10101010	10101010	10101010
ram[2]	undefined	undefined	undefined	11110000	11110000	11110000
dout	undefined	10101010	10101010	11110000	11110000	10101010

Key Moments - 3 Insights

Why does dout update even when write_enable (we) is 0?

Because the RAM reads the data at the given address every clock edge regardless of write_enable, as shown in rows 2, 4, and 5 of the execution_table.

What happens if write_enable is 1 and we write to an address?

The data at that address is updated with din on the clock edge, and dout outputs the new data immediately, as seen in rows 1 and 3.

Why is dout updated after writing and reading in the same clock cycle?

Because the design reads the RAM at the same clock edge after writing, so dout reflects the latest data at the address, demonstrated in the execution_table steps.

Visual Quiz - 3 Questions

Look at the execution_table at step 2. What is the value of dout?

A 11110000

B XXXXXXXX

C 10101010

D 00000000

💡 Hint

Check the 'dout (output)' column at step 2 in the execution_table.

At which step does the RAM write 11110000 to address 2?

A Step 1

B Step 3

C Step 4

D Step 5

💡 Hint

Look at the 'Action' column for the write operation to address 2 in the execution_table.

If write_enable (we) is always 0, what will dout show after multiple clock cycles?

A It will show data at the current address without changes.

B It will always be undefined.

C It will show the last written data.

D It will show random data.

💡 Hint

Refer to variable_tracker and execution_table rows where we=0 and observe dout values.

Concept Snapshot

Single-port RAM design in Verilog:
- Uses one port for read/write.
- On clock edge, if write_enable is 1, write data to address.
- Always read data at address and output it.
- Synchronous operation with clk.
- RAM size and data width defined by reg array.

Full Transcript

This visual execution traces a single-port RAM design in Verilog. The RAM has one port used for both reading and writing. On each rising clock edge, the design checks if write_enable is high. If yes, it writes the input data to the specified address. Regardless of writing, it reads the data at the address and outputs it. The execution table shows five clock cycles with different write_enable and addresses. The variable tracker shows how RAM contents and output change over time. Key moments clarify why output updates even when not writing and how writing affects RAM. The quiz tests understanding of output values and write timing. This design is synchronous and simple, suitable for beginners learning RAM behavior in hardware description languages.

Practice

1. What is the main characteristic of a single-port RAM in Verilog?

easy

A. It stores data without any clock or control signals.

B. It can read and write data simultaneously on separate ports.

C. It uses one address line for both reading and writing operations.

D. It requires two clocks for read and write operations.

Solution

1. Step 1: Understand single-port RAM basics

   Single-port RAM has only one address line used for both reading and writing data.

2. Step 2: Compare with other RAM types

   Unlike dual-port RAM, it cannot perform read and write simultaneously on different ports.

3. Final Answer:

   It uses one address line for both reading and writing operations. -> Option C

4. Quick Check:

   Single-port RAM = one address line for read/write [OK]

Hint: Single-port RAM uses one address for both read and write [OK]

Common Mistakes:

• Thinking it can read and write at the same time
• Assuming it needs two clocks
• Believing it works without a clock

2. Which of the following is the correct Verilog syntax to declare a 256x8 single-port RAM memory array?

easy

A. wire [7:0] mem [255:0];

B. memory [7:0] mem [0:255];

C. reg mem [7:0] [0:255];

D. reg [7:0] mem [0:255];

Solution

1. Step 1: Understand Verilog memory declaration

   Memory arrays are declared as reg [width-1:0] name [address_range]; for RAM.

2. Step 2: Check each option

   reg [7:0] mem [0:255]; correctly declares 256 locations (0 to 255) each 8 bits wide. wire [7:0] mem [255:0]; uses wire which is incorrect for RAM storage. reg mem [7:0] [0:255]; reverses dimensions. memory [7:0] mem [0:255]; uses invalid keyword.

3. Final Answer:

   reg [7:0] mem [0:255]; -> Option D

4. Quick Check:

   RAM declaration = reg [7:0] mem [0:255] [OK]

Hint: Use reg with [width-1:0] and address range [OK]

Common Mistakes:

• Using wire instead of reg for RAM
• Swapping width and address range
• Using invalid keywords like memory

3. Given the following Verilog code snippet for a single-port RAM, what is the value of data_out after the clock edge if we = 1, addr = 3, and data_in = 8'hAA?

reg [7:0] mem [0:7];
always @(posedge clk) begin
  if (we) mem[addr] <= data_in;
  data_out <= mem[addr];
end

medium

A. 8'hAA

B. Previous value stored at mem[3]

C. 8'h00

D. Undefined (X)

Solution

1. Step 1: Analyze write and read order in always block

   The write happens first: if we=1, mem[3] is updated with 8'hAA. Then data_out is assigned mem[3].

2. Step 2: Understand non-blocking assignment timing

   Non-blocking assignments update after the always block finishes, so data_out reads the old value of mem[3] before write.

3. Final Answer:

   Previous value stored at mem[3] -> Option B

4. Quick Check:

   Non-blocking write then read = old value [OK]

Hint: Non-blocking writes update after reads in same clock [OK]

Common Mistakes:

• Assuming data_out immediately shows new data_in
• Confusing blocking and non-blocking assignments
• Ignoring timing of memory update

4. Identify the error in this single-port RAM Verilog code snippet:

reg [7:0] mem [0:15];
always @(posedge clk) begin
  if (we)
    mem[addr] = data_in;
  else
    data_out = mem[addr];
end

medium

A. Using blocking assignments (=) instead of non-blocking (<=) inside always block.

B. Memory size declaration is incorrect.

C. Missing reset signal for memory initialization.

D. Address width is not declared.

Solution

1. Step 1: Check assignment types in sequential always block

   Inside clocked always blocks, non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Verify other code parts

   Memory size and address width are not shown but not necessarily errors here. Reset is optional.

3. Final Answer:

   Using blocking assignments (=) instead of non-blocking (<=) inside always block. -> Option A

4. Quick Check:

   Use <= in clocked always blocks [OK]

Hint: Use <= for sequential logic inside always @(posedge clk) [OK]

Common Mistakes:

• Using = instead of <= in clocked blocks
• Assuming reset is mandatory
• Ignoring address width declaration

5. You want to design a single-port RAM in Verilog that supports synchronous write and asynchronous read. Which code snippet correctly implements this behavior?

hard

A. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
end
assign data_out = mem[addr];

B. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
data_out <= mem[addr];
end

C. reg [7:0] mem [0:15];
always @(addr or we or data_in) begin
if (we) mem[addr] = data_in;
end
assign data_out = mem[addr];

D. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] = data_in;
end
always @(addr) begin
data_out = mem[addr];
end

Solution

1. Step 1: Understand synchronous write and asynchronous read

   Write happens on clock edge with write enable; read happens anytime from memory asynchronously.

2. Step 2: Analyze each code snippet

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] <= data_in;
   end
   assign data_out = mem[addr];

   uses clocked always block for write and continuous assignment for asynchronous read, which is correct.

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] <= data_in;
     data_out <= mem[addr];
   end

   reads synchronously.

   reg [7:0] mem [0:15];
   always @(addr or we or data_in) begin
     if (we) mem[addr] = data_in;
   end
   assign data_out = mem[addr];

   uses combinational always block for write, which is incorrect.

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] = data_in;
   end
   always @(addr) begin
     data_out = mem[addr];
   end

   uses blocking assignment in clocked block and asynchronous read in always block, which is not standard.

3. Final Answer:

   Option A code snippet -> Option A

4. Quick Check:

   Synchronous write + async read = clocked write + assign read [OK]

Hint: Use clocked block for write, continuous assign for async read [OK]

Common Mistakes:

• Reading memory synchronously instead of asynchronously
• Using blocking assignments in clocked blocks
• Trying to write memory combinationally