Single-port RAM design in Verilog - Step-by-Step Execution

Concept Flow - Single-port RAM design

Start

↓

Check write_enable?

No→Read data at address

|Yes↓

Write data at address

↓

Output data

↓

End

The RAM checks if write is enabled; if yes, it writes data to the address, else it reads data from the address and outputs it.

Execution Sample

Verilog

module single_port_ram(
  input clk,
  input we,
  input [3:0] addr,
  input [7:0] din,
  output reg [7:0] dout
);
  reg [7:0] ram [0:15];
  always @(posedge clk) begin
    if (we) begin
      ram[addr] <= din;
      dout <= din;
    end else begin
      dout <= ram[addr];
    end
  end
endmodule

This code defines a 16x8-bit single-port RAM with synchronous write and read on clock edge.

Execution Table

Step	clk edge	write_enable (we)	addr	din	Action	dout (output)
1	rising	1	4	10101010	Write 10101010 at addr 4; Read addr 4	10101010
2	rising	0	4	XXXXXXXX	No write; Read addr 4	10101010
3	rising	1	2	11110000	Write 11110000 at addr 2; Read addr 2	11110000
4	rising	0	2	XXXXXXXX	No write; Read addr 2	11110000
5	rising	0	4	XXXXXXXX	No write; Read addr 4	10101010

💡 Simulation ends after 5 clock cycles demonstrating write and read operations.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
ram[4]	undefined	10101010	10101010	10101010	10101010	10101010
ram[2]	undefined	undefined	undefined	11110000	11110000	11110000
dout	undefined	10101010	10101010	11110000	11110000	10101010

Key Moments - 3 Insights

Why does dout update even when write_enable (we) is 0?

Because the RAM reads the data at the given address every clock edge regardless of write_enable, as shown in rows 2, 4, and 5 of the execution_table.

What happens if write_enable is 1 and we write to an address?

The data at that address is updated with din on the clock edge, and dout outputs the new data immediately, as seen in rows 1 and 3.

Why is dout updated after writing and reading in the same clock cycle?

Because the design reads the RAM at the same clock edge after writing, so dout reflects the latest data at the address, demonstrated in the execution_table steps.

Visual Quiz - 3 Questions

Look at the execution_table at step 2. What is the value of dout?

A 11110000

B XXXXXXXX

C 10101010

D 00000000

💡 Hint

Check the 'dout (output)' column at step 2 in the execution_table.

At which step does the RAM write 11110000 to address 2?

A Step 1

B Step 3

C Step 4

D Step 5

💡 Hint

Look at the 'Action' column for the write operation to address 2 in the execution_table.

If write_enable (we) is always 0, what will dout show after multiple clock cycles?

A It will show data at the current address without changes.

B It will always be undefined.

C It will show the last written data.

D It will show random data.

💡 Hint

Refer to variable_tracker and execution_table rows where we=0 and observe dout values.

Concept Snapshot

Single-port RAM design in Verilog:
- Uses one port for read/write.
- On clock edge, if write_enable is 1, write data to address.
- Always read data at address and output it.
- Synchronous operation with clk.
- RAM size and data width defined by reg array.

Full Transcript

This visual execution traces a single-port RAM design in Verilog. The RAM has one port used for both reading and writing. On each rising clock edge, the design checks if write_enable is high. If yes, it writes the input data to the specified address. Regardless of writing, it reads the data at the address and outputs it. The execution table shows five clock cycles with different write_enable and addresses. The variable tracker shows how RAM contents and output change over time. Key moments clarify why output updates even when not writing and how writing affects RAM. The quiz tests understanding of output values and write timing. This design is synchronous and simple, suitable for beginners learning RAM behavior in hardware description languages.