Single-port RAM design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this single-port RAM read operation?

Consider this Verilog code snippet for a single-port RAM. What value will be read on data_out after the clock edge if addr = 3 and the memory was initialized with mem[3] = 8'hA5?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_out;
reg [2:0] addr;

always @(posedge clk) begin
  data_out <= mem[addr];
end

A data_out = 8'hA5

B data_out = 8'h00

C data_out = 8'hFF

D data_out = undefined (X)

💡 Hint

Remember that on the positive clock edge, the data at the address is loaded into data_out.

The code reads the memory at the given address on the rising clock edge. Since mem[3] was initialized to 8'hA5, data_out will be assigned that value.

❓ Predict Output

intermediate

What is the value of mem[5] after this write operation?

Given this single-port RAM write code, what will be the value stored in mem[5] after the clock edge if addr = 5, data_in = 8'h3C, and we = 1?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_in;
reg [2:0] addr;
reg we;

always @(posedge clk) begin
  if (we) begin
    mem[addr] <= data_in;
  end
end

A mem[5] = 8'h3C

B mem[5] = 8'h00

C mem[5] = undefined (X)

D mem[5] = previous value (unchanged)

💡 Hint

Write enable (we) controls whether the memory is updated on the clock edge.

When we is 1, the memory at the address is updated with data_in on the rising clock edge. So mem[5] becomes 8'h3C.

🔧 Debug

advanced

Why does this single-port RAM code cause a synthesis error?

Examine this single-port RAM code. Why will it cause a synthesis error or not work as intended?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_out;
reg [2:0] addr;
reg we;

always @(posedge clk) begin
  if (we) begin
    mem[addr] <= data_out;
  end else begin
    data_out <= mem[addr];
  end
end

A Because mem is not declared as a wire

B Because data_out is used as input for writing, causing read-write conflict on the same port

C Because the clock signal is missing from sensitivity list

D Because the address width is too small for the memory size

💡 Hint

Think about what happens when you try to read and write the same memory location on the same clock edge.

The code tries to write data_out into mem and read mem into data_out on the same clock edge, causing a conflict on the single port RAM which cannot read and write simultaneously.

📝 Syntax

advanced

Which option correctly declares a 16x8 single-port RAM in Verilog?

Select the correct Verilog declaration for a single-port RAM with 16 addresses and 8-bit data width.

A wire [7:0] mem [0:15];

B reg [15:0] mem [0:7];

C reg [7:0] mem [0:15];

D reg mem [7:0] [0:15];

💡 Hint

Remember the syntax for declaring memory arrays in Verilog: data width first, then address range.

Option C correctly declares a memory with 16 addresses (0 to 15) each 8 bits wide. Option C swaps width and depth. Option C uses wire which is not allowed for memory. Option C has invalid syntax.

🚀 Application

expert

How many clock cycles does it take for data_out to reflect a write at address 4?

In a synchronous single-port RAM design, if you write data to address 4 at clock cycle N, at which clock cycle will a read from address 4 return the new data on data_out?

A Immediately, combinationally without clock delay

B At clock cycle N (same cycle as write)

C At clock cycle N+2 (two cycles after write)

D At clock cycle N+1 (one cycle after write)

💡 Hint

Think about synchronous RAM behavior and when data is updated and available on output.

In synchronous single-port RAM, writes happen on the clock edge, but the new data is available on the output only on the next clock cycle when the read occurs.