Single-port RAM design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this single-port RAM read operation?

Consider this Verilog code snippet for a single-port RAM. What value will be read on data_out after the clock edge if addr = 3 and the memory was initialized with mem[3] = 8'hA5?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_out;
reg [2:0] addr;

always @(posedge clk) begin
  data_out <= mem[addr];
end

A data_out = 8'hA5

B data_out = 8'h00

C data_out = 8'hFF

D data_out = undefined (X)

💡 Hint

Remember that on the positive clock edge, the data at the address is loaded into data_out.

The code reads the memory at the given address on the rising clock edge. Since mem[3] was initialized to 8'hA5, data_out will be assigned that value.

❓ Predict Output

intermediate

What is the value of mem[5] after this write operation?

Given this single-port RAM write code, what will be the value stored in mem[5] after the clock edge if addr = 5, data_in = 8'h3C, and we = 1?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_in;
reg [2:0] addr;
reg we;

always @(posedge clk) begin
  if (we) begin
    mem[addr] <= data_in;
  end
end

A mem[5] = 8'h3C

B mem[5] = 8'h00

C mem[5] = undefined (X)

D mem[5] = previous value (unchanged)

💡 Hint

Write enable (we) controls whether the memory is updated on the clock edge.

When we is 1, the memory at the address is updated with data_in on the rising clock edge. So mem[5] becomes 8'h3C.

🔧 Debug

advanced

Why does this single-port RAM code cause a synthesis error?

Examine this single-port RAM code. Why will it cause a synthesis error or not work as intended?

Verilog

reg [7:0] mem [0:7];
reg [7:0] data_out;
reg [2:0] addr;
reg we;

always @(posedge clk) begin
  if (we) begin
    mem[addr] <= data_out;
  end else begin
    data_out <= mem[addr];
  end
end

A Because mem is not declared as a wire

B Because data_out is used as input for writing, causing read-write conflict on the same port

C Because the clock signal is missing from sensitivity list

D Because the address width is too small for the memory size

💡 Hint

Think about what happens when you try to read and write the same memory location on the same clock edge.

The code tries to write data_out into mem and read mem into data_out on the same clock edge, causing a conflict on the single port RAM which cannot read and write simultaneously.

📝 Syntax

advanced

Which option correctly declares a 16x8 single-port RAM in Verilog?

Select the correct Verilog declaration for a single-port RAM with 16 addresses and 8-bit data width.

A wire [7:0] mem [0:15];

B reg [15:0] mem [0:7];

C reg [7:0] mem [0:15];

D reg mem [7:0] [0:15];

💡 Hint

Remember the syntax for declaring memory arrays in Verilog: data width first, then address range.

Option C correctly declares a memory with 16 addresses (0 to 15) each 8 bits wide. Option C swaps width and depth. Option C uses wire which is not allowed for memory. Option C has invalid syntax.

🚀 Application

expert

How many clock cycles does it take for data_out to reflect a write at address 4?

In a synchronous single-port RAM design, if you write data to address 4 at clock cycle N, at which clock cycle will a read from address 4 return the new data on data_out?

A Immediately, combinationally without clock delay

B At clock cycle N (same cycle as write)

C At clock cycle N+2 (two cycles after write)

D At clock cycle N+1 (one cycle after write)

💡 Hint

Think about synchronous RAM behavior and when data is updated and available on output.

In synchronous single-port RAM, writes happen on the clock edge, but the new data is available on the output only on the next clock cycle when the read occurs.

Practice

1. What is the main characteristic of a single-port RAM in Verilog?

easy

A. It stores data without any clock or control signals.

B. It can read and write data simultaneously on separate ports.

C. It uses one address line for both reading and writing operations.

D. It requires two clocks for read and write operations.

Solution

1. Step 1: Understand single-port RAM basics

   Single-port RAM has only one address line used for both reading and writing data.

2. Step 2: Compare with other RAM types

   Unlike dual-port RAM, it cannot perform read and write simultaneously on different ports.

3. Final Answer:

   It uses one address line for both reading and writing operations. -> Option C

4. Quick Check:

   Single-port RAM = one address line for read/write [OK]

Hint: Single-port RAM uses one address for both read and write [OK]

Common Mistakes:

• Thinking it can read and write at the same time
• Assuming it needs two clocks
• Believing it works without a clock

2. Which of the following is the correct Verilog syntax to declare a 256x8 single-port RAM memory array?

easy

A. wire [7:0] mem [255:0];

B. memory [7:0] mem [0:255];

C. reg mem [7:0] [0:255];

D. reg [7:0] mem [0:255];

Solution

1. Step 1: Understand Verilog memory declaration

   Memory arrays are declared as reg [width-1:0] name [address_range]; for RAM.

2. Step 2: Check each option

   reg [7:0] mem [0:255]; correctly declares 256 locations (0 to 255) each 8 bits wide. wire [7:0] mem [255:0]; uses wire which is incorrect for RAM storage. reg mem [7:0] [0:255]; reverses dimensions. memory [7:0] mem [0:255]; uses invalid keyword.

3. Final Answer:

   reg [7:0] mem [0:255]; -> Option D

4. Quick Check:

   RAM declaration = reg [7:0] mem [0:255] [OK]

Hint: Use reg with [width-1:0] and address range [OK]

Common Mistakes:

• Using wire instead of reg for RAM
• Swapping width and address range
• Using invalid keywords like memory

3. Given the following Verilog code snippet for a single-port RAM, what is the value of data_out after the clock edge if we = 1, addr = 3, and data_in = 8'hAA?

reg [7:0] mem [0:7];
always @(posedge clk) begin
  if (we) mem[addr] <= data_in;
  data_out <= mem[addr];
end

medium

A. 8'hAA

B. Previous value stored at mem[3]

C. 8'h00

D. Undefined (X)

Solution

1. Step 1: Analyze write and read order in always block

   The write happens first: if we=1, mem[3] is updated with 8'hAA. Then data_out is assigned mem[3].

2. Step 2: Understand non-blocking assignment timing

   Non-blocking assignments update after the always block finishes, so data_out reads the old value of mem[3] before write.

3. Final Answer:

   Previous value stored at mem[3] -> Option B

4. Quick Check:

   Non-blocking write then read = old value [OK]

Hint: Non-blocking writes update after reads in same clock [OK]

Common Mistakes:

• Assuming data_out immediately shows new data_in
• Confusing blocking and non-blocking assignments
• Ignoring timing of memory update

4. Identify the error in this single-port RAM Verilog code snippet:

reg [7:0] mem [0:15];
always @(posedge clk) begin
  if (we)
    mem[addr] = data_in;
  else
    data_out = mem[addr];
end

medium

A. Using blocking assignments (=) instead of non-blocking (<=) inside always block.

B. Memory size declaration is incorrect.

C. Missing reset signal for memory initialization.

D. Address width is not declared.

Solution

1. Step 1: Check assignment types in sequential always block

   Inside clocked always blocks, non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Verify other code parts

   Memory size and address width are not shown but not necessarily errors here. Reset is optional.

3. Final Answer:

   Using blocking assignments (=) instead of non-blocking (<=) inside always block. -> Option A

4. Quick Check:

   Use <= in clocked always blocks [OK]

Hint: Use <= for sequential logic inside always @(posedge clk) [OK]

Common Mistakes:

• Using = instead of <= in clocked blocks
• Assuming reset is mandatory
• Ignoring address width declaration

5. You want to design a single-port RAM in Verilog that supports synchronous write and asynchronous read. Which code snippet correctly implements this behavior?

hard

A. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
end
assign data_out = mem[addr];

B. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
data_out <= mem[addr];
end

C. reg [7:0] mem [0:15];
always @(addr or we or data_in) begin
if (we) mem[addr] = data_in;
end
assign data_out = mem[addr];

D. reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we) mem[addr] = data_in;
end
always @(addr) begin
data_out = mem[addr];
end

Solution

1. Step 1: Understand synchronous write and asynchronous read

   Write happens on clock edge with write enable; read happens anytime from memory asynchronously.

2. Step 2: Analyze each code snippet

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] <= data_in;
   end
   assign data_out = mem[addr];

   uses clocked always block for write and continuous assignment for asynchronous read, which is correct.

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] <= data_in;
     data_out <= mem[addr];
   end

   reads synchronously.

   reg [7:0] mem [0:15];
   always @(addr or we or data_in) begin
     if (we) mem[addr] = data_in;
   end
   assign data_out = mem[addr];

   uses combinational always block for write, which is incorrect.

   reg [7:0] mem [0:15];
   always @(posedge clk) begin
     if (we) mem[addr] = data_in;
   end
   always @(addr) begin
     data_out = mem[addr];
   end

   uses blocking assignment in clocked block and asynchronous read in always block, which is not standard.

3. Final Answer:

   Option A code snippet -> Option A

4. Quick Check:

   Synchronous write + async read = clocked write + assign read [OK]

Hint: Use clocked block for write, continuous assign for async read [OK]

Common Mistakes:

• Reading memory synchronously instead of asynchronously
• Using blocking assignments in clocked blocks
• Trying to write memory combinationally