Single-port RAM design in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a single-port RAM in digital design?

A single-port RAM is a memory block with one port that can be used for either reading or writing data, but not both at the same time.

beginner

In Verilog, which signals are typically used to control a single-port RAM?

Address (to select memory location), Data input (for writing), Data output (for reading), Write enable (to control write operation), and Clock (to synchronize operations).

beginner

Explain the role of the write enable signal in a single-port RAM.

The write enable signal determines if the RAM should write data to the memory at the given address on the clock edge. If it is low, the RAM performs a read operation instead.

intermediate

What happens if you try to read and write at the same address simultaneously in a single-port RAM?

Since there is only one port, simultaneous read and write at the same address is not possible. The operation depends on the write enable signal and clock timing, usually prioritizing write or read based on design.

beginner

Show a simple Verilog code snippet for a 16x8 single-port RAM.

module single_port_ram ( input logic clk, input logic we, input logic [3:0] addr, input logic [7:0] din, output logic [7:0] dout ); logic [7:0] mem [0:15]; always_ff @(posedge clk) begin if (we) mem[addr] <= din; dout <= mem[addr]; end endmodule

What does the 'we' signal control in a single-port RAM?

A Whether to write data to memory

B The clock speed

C The address selection

D The output data

The 'we' (write enable) signal controls if the RAM writes data to the memory location on the clock edge.

In a single-port RAM, how many addresses can be accessed at the same time?

A Four

B Two

C Multiple

D One

Single-port RAM allows access to only one address at a time for either read or write.

Which Verilog construct is commonly used to model synchronous RAM behavior?

A assign

B always_comb

C always_ff @(posedge clk)

D initial

The 'always_ff @(posedge clk)' block models behavior that happens on the clock's rising edge, suitable for synchronous RAM.

What is the size of the memory in a 16x8 single-port RAM?

A 16 locations, each 8 bits wide

B 8 locations, each 16 bits wide

C 24 bits total

D 128 bits total

16x8 means 16 memory locations, each storing 8 bits.

If 'we' is low, what operation does the single-port RAM perform?

A Write

B Read

C Reset

D Idle

When 'we' is low, the RAM performs a read operation.

Describe how a single-port RAM works and how you control reading and writing in Verilog.

Think about how the write enable signal changes the RAM behavior on the clock.

Write a simple Verilog module for a 16x8 single-port RAM and explain each part.

Focus on how the memory array is declared and updated inside the clocked block.