Single-port RAM design in Verilog - Mini Project: Build & Apply

Single-port RAM Design in Verilog

📖 Scenario: You are designing a simple memory module for a small digital system. This memory will store 8-bit data values and have 16 address locations. You will create a single-port RAM where you can read or write data at one address at a time.

🎯 Goal: Build a single-port RAM module in Verilog with 16 addresses and 8-bit data width. You will set up the memory, add control signals, implement the read/write logic, and finally display the stored data at a given address.

📋 What You'll Learn

Create a memory array with 16 locations, each 8 bits wide

Add input signals for address, data input, write enable, and clock

Implement logic to write data to memory on clock edge when write enable is high

Implement logic to read data from memory at the given address

Print the output data value after a write and read operation

💡 Why This Matters

🌍 Real World

Single-port RAM modules are used in small embedded systems and FPGA designs to store temporary data or configuration settings.

💼 Career

Understanding RAM design is important for hardware engineers working on digital circuit design, FPGA programming, and embedded system development.

1

Create the memory array

Create a reg array called mem with 16 locations, each 8 bits wide.

Verilog

# Your code here

Need a hint?

Use reg [7:0] mem [0:15]; to declare the memory array.

2

Add input and output signals

Declare inputs input [3:0] addr, input [7:0] data_in, input we, input clk, and output output reg [7:0] data_out.

Verilog

reg [7:0] mem [0:15];
// Declare inputs addr, data_in, we, clk and output data_out
# Your code here

Need a hint?

Use input and output reg keywords to declare signals.

3

Implement write and read logic

Write an always @(posedge clk) block that writes data_in to mem[addr] when we is high, and always updates data_out with mem[addr].

Verilog

reg [7:0] mem [0:15];
input [3:0] addr;
input [7:0] data_in;
input we;
input clk;
output reg [7:0] data_out;

// Add always block for write and read
# Your code here

Need a hint?

Use a clocked always block with an if statement for write enable.

4

Display the output data

Write a testbench code snippet that sets addr = 4, data_in = 8'hA5, we = 1, toggles clk, then sets we = 0 and toggles clk again. Finally, print data_out.

Verilog

reg [7:0] mem [0:15];
input [3:0] addr;
input [7:0] data_in;
input we;
input clk;
output reg [7:0] data_out;

always @(posedge clk) begin
    if (we) begin
        mem[addr] <= data_in;
    end
    data_out <= mem[addr];
end

// Testbench code to write and read, then print data_out
# Your code here

Need a hint?

Use $display to print the data_out value after clock edges.