Single-port RAM design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 256x8 single-port RAM memory array.

Verilog

reg [7:0] memory_array [0:[1]];

Drag options to blanks, or click blank then click option'

A512

B256

C255

D128

Attempts:

3 left

💡 Hint

Common Mistakes

Using 256 as the highest index instead of 255.

Confusing the data width with the number of locations.

The memory array has 256 locations indexed from 0 to 255, so the highest index is 255.

2fill in blank

medium

Complete the code to write data into the RAM on the rising edge of the clock when write enable is high.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    memory_array[address] <= data_in;
  end
end

Drag options to blanks, or click blank then click option'

Areset

Benable

Cread_enable

Dwrite_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using read_enable instead of write_enable.

Using reset signal in the write condition.

The write operation happens only when the write enable signal is high.

3fill in blank

hard

Fix the error in the code to correctly read data from the RAM asynchronously.

Verilog

assign data_out = memory_array[[1]];

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Aaddress

Bdata_in

Cwrite_enable

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_in instead of address for reading.

Using clock signal as index.

The output data is read from the memory at the given address.

4fill in blank

hard

Fill both blanks to complete the synchronous write and asynchronous read logic.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    memory_array[address] <= data_in;
  end
end

assign data_out = memory_array[[2]];

Drag options to blanks, or click blank then click option'

Awrite_enable

Bread_enable

Caddress

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using read_enable in the write condition.

Using data_in as the read address.

Write happens when write_enable is high on clock edge, and read uses the address signal.

5fill in blank

hard

Fill all three blanks to complete the single-port RAM module with input and output ports.

Verilog

module single_port_ram(
  input wire clk,
  input wire [1],
  input wire [7:0] data_in,
  input wire [7:0] [2],
  output wire [7:0] [3]
);

reg [7:0] memory_array [0:255];

always @(posedge clk) begin
  if (write_enable) begin
    memory_array[address] <= data_in;
  end
end

assign data_out = memory_array[address];

endmodule

Drag options to blanks, or click blank then click option'

Awrite_enable

Baddress

Cdata_out

Dread_enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using read_enable instead of write_enable.

Confusing data_in and data_out port names.

The module ports include write_enable signal, address input, and data_out output.