Sequence detector FSM in Verilog - Step-by-Step Execution

Concept Flow - Sequence detector FSM

Start: Wait for input bit

↓

Check current bit

↓

Update FSM state

↓

Check if sequence detected?

No→Wait for next bit

Yes↓

Output: Sequence detected signal

↓

Reset or continue detecting

The FSM reads input bits one by one, updates its state based on the sequence progress, and signals when the target sequence is detected.

Execution Sample

Verilog

module seq_detector(
  input clk, reset, in_bit,
  output reg detected
);
  // FSM states and logic here
endmodule

This Verilog module detects a specific bit sequence on input 'in_bit' and sets 'detected' high when found.

Execution Table

Step	Input bit	Current State	Next State	Detected Output
1	1	S0	S1	0
2	0	S1	S2	0
3	1	S2	S3	0
4	1	S3	S1	1
5	0	S1	S2	0
6	1	S2	S3	0
7	0	S3	S0	0
8	1	S0	S1	0
Exit	-	-	-	Sequence detection ends or continues

💡 FSM continues reading bits until reset; detection output signals when sequence matched.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7	After Step 8
Current State	S0	S1	S2	S3	S1	S2	S3	S0	S1
Detected Output	0	0	0	0	1	0	0	0	0

Key Moments - 2 Insights

Why does the FSM go back to state S1 after detecting the sequence instead of resetting to S0?

The FSM returns to S1 to allow overlapping sequences detection, as shown in execution_table step 4 where next state is S1 after detection.

Why is the detected output '1' only at step 4 and not at other steps?

Detected output is '1' only when the full sequence is matched, which happens at step 4 according to the execution_table.

Visual Quiz - 3 Questions

Look at the execution_table, what is the FSM state after input bit '0' at step 2?

A S1

B S2

C S0

D S3

💡 Hint

Check the 'Next State' column at step 2 in the execution_table.

At which step does the FSM output 'detected' signal as '1'?

A Step 4

B Step 5

C Step 3

D Step 6

💡 Hint

Look at the 'Detected Output' column in the execution_table.

If the input bit at step 7 was '1' instead of '0', what would be the next state?

A S0

B S2

C S1

D S3

💡 Hint

Refer to the pattern of state transitions in the execution_table and variable_tracker.

Concept Snapshot

Sequence Detector FSM in Verilog:
- Reads input bits sequentially
- Updates state based on partial sequence matched
- Outputs 'detected' when full sequence found
- Supports overlapping sequences by smart state transitions
- Uses states like S0, S1, S2, S3 to track progress

Full Transcript

This visual execution shows a sequence detector FSM in Verilog. The FSM starts at state S0 and reads input bits one by one. Each input bit causes a state update reflecting how much of the target sequence has been matched. When the full sequence is detected, the FSM outputs a 'detected' signal set to 1. The FSM then transitions to a state that allows detection of overlapping sequences. The execution table traces each step with input bit, current state, next state, and output. The variable tracker shows how the FSM state and output change after each input. Key moments clarify why the FSM returns to certain states and when the output is set. The quiz tests understanding of state transitions and output timing. This helps beginners see exactly how the FSM processes inputs and signals detection.