Sequence detector FSM in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the input signal for the FSM.

Verilog

module seq_detector(input clk, input rst, input [1], output reg detected);

Drag options to blanks, or click blank then click option'

Ain_bit

Binput_bit

Cbit_in

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using a signal name that is not declared in the module inputs.

Confusing output signals with input signals.

The input signal is named data_in to represent the incoming bit stream.

2fill in blank

medium

Complete the code to define the state type using an enum.

Verilog

typedef enum logic [1:0] {IDLE, [1], MATCHED, ERROR} state_t;

Drag options to blanks, or click blank then click option'

ASEEN1

BCHECK

CDETECT

DWAIT

Attempts:

3 left

💡 Hint

Common Mistakes

Using generic state names that don't reflect the sequence detection.

Choosing states that are not part of the FSM design.

The state SEEN1 represents the FSM having detected the first bit of the sequence.

3fill in blank

hard

Fix the error in the always block sensitivity list.

Verilog

always_ff @(posedge clk or [1]) begin

Drag options to blanks, or click blank then click option'

Aposedge rst

Bnegedge rst

Cnegedge clk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge rst when reset is active low.

Omitting the reset signal from the sensitivity list.

The reset signal is usually active low, so the sensitivity list uses negedge rst.

4fill in blank

hard

Fill both blanks to complete the state transition condition.

Verilog

if (current_state == IDLE && data_in == [1]) next_state = [2];

Drag options to blanks, or click blank then click option'

A1

B0

CSEEN1

DMATCHED

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing input bit values for transitions.

Assigning wrong next state for the given input.

When in IDLE state and input bit is 0, FSM moves to SEEN1 state.

5fill in blank

hard

Fill all three blanks to complete the output logic for sequence detection.

Verilog

always_ff @(posedge clk or negedge rst) begin
  if (!rst) detected <= 0;
  else if (current_state == [1] && data_in == [2]) detected <= [3];
  else detected <= 0;
end

Drag options to blanks, or click blank then click option'

ASEEN1

BMATCHED

C1

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Setting output high in wrong states.

Using incorrect input bit value for detection.

The output detected is set to 1 when the FSM is in MATCHED state and input bit is 1.