Sequence detector FSM in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Sequence Detector FSM in Verilog?

A Sequence Detector FSM is a finite state machine designed to detect a specific sequence of bits in a serial input stream. It outputs a signal when the sequence is found.

beginner

What are the main components of a Sequence Detector FSM in Verilog?

The main components are: states (to remember progress), inputs (bit stream), outputs (detection signal), and state transitions (rules to move between states based on input).

intermediate

How do you represent states in a Verilog FSM for sequence detection?

States are usually represented using parameters or localparams with unique binary values. For example: parameter S0 = 2'b00, S1 = 2'b01, etc.

intermediate

Why is it important to handle overlapping sequences in a Sequence Detector FSM?

Handling overlapping sequences allows the FSM to detect sequences that share bits with previous detections without missing any occurrences.

beginner

What is the role of the clock and reset signals in a Verilog Sequence Detector FSM?

The clock synchronizes state changes, ensuring the FSM updates on each clock cycle. The reset initializes the FSM to a known start state.

In a sequence detector FSM, what does the output signal usually indicate?

A The FSM is in the initial state

B The sequence has been detected

C The input bit is zero

D The clock is running

The output signal goes high when the FSM detects the target sequence in the input stream.

How are states typically defined in Verilog for FSMs?

A Using variables that change randomly

B Using comments

C Using functions

D Using parameters or localparams with unique binary values

States are defined with parameters or localparams to assign unique binary codes for clarity and synthesis.

Why do we need a reset signal in a sequence detector FSM?

A To initialize the FSM to a known start state

B To stop the clock

C To change the input sequence

D To increase output frequency

Reset sets the FSM to a known state so it can start detecting sequences correctly.

What is the purpose of handling overlapping sequences in FSM design?

A To detect sequences that share bits without missing any

B To slow down the FSM

C To ignore repeated sequences

D To reset the FSM automatically

Overlapping handling ensures the FSM detects sequences even if they start before the previous one ends.

Which signal controls when the FSM updates its state?

A Output signal

B Reset signal

C Clock signal

D Input bit

The clock signal synchronizes state changes in the FSM.

Explain how a sequence detector FSM works in Verilog, including states, inputs, outputs, and transitions.

Think about how the FSM moves through states based on input bits to find a sequence.

Describe why handling overlapping sequences is important in a sequence detector FSM and how it affects state transitions.

Consider what happens when a new sequence starts before the previous one finishes.

Practice

1.

What is the main purpose of a sequence detector FSM in Verilog?

easy

A. To perform arithmetic operations on input data

B. To detect a specific pattern of bits in a serial input stream

C. To generate random numbers

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM watches input bits and changes states based on the pattern seen.

2. Step 2: Identify purpose

   Its main job is to find a specific bit pattern in a stream and signal when found.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option B

4. Quick Check:

   Sequence detector FSM = pattern detection [OK]

Hint: FSMs track input patterns to signal matches [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does arithmetic

2.

Which of the following is the correct way to declare a state type for a sequence detector FSM in Verilog?

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

easy

A. typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

B. enum state_t {S0, S1, S2, S3};

C. typedef enum {S0, S1, S2, S3} state_t;

D. state_t enum logic [1:0] {S0, S1, S2, S3};

Solution

1. Step 1: Check Verilog enum syntax

   SystemVerilog uses 'typedef enum logic [width] {states} name;' to define state types.

2. Step 2: Match correct syntax

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; matches this syntax exactly, defining 2-bit logic states with typedef.

3. Final Answer:

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; -> Option A

4. Quick Check:

   Correct enum typedef syntax = typedef enum logic [1:0] {S0, S1, S2, S3} state_t; [OK]

Hint: Use 'typedef enum logic [width]' for states in Verilog [OK]

Common Mistakes:

• Omitting 'typedef' keyword
• Missing logic width specification
• Incorrect order of keywords

3.

Given the following Verilog snippet for a sequence detector FSM that detects "101":

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: state <= (in == 1) ? S1 : S0;
      S1: state <= (in == 0) ? S2 : S1;
      S2: state <= (in == 1) ? S3 : S0;
      S3: state <= S0;
    endcase
  end
end

assign detected = (state == S3);

If the input sequence is 1 0 1, what will be the value of detected after the last bit?

medium

A. Undefined

B. 0

C. 1

D. Depends on reset

Solution

1. Step 1: Trace FSM states for input 1,0,1

   Start at S0. Input 1 moves to S1. Input 0 moves to S2. Input 1 moves to S3.

2. Step 2: Check output at S3

   Detected is assigned 1 when state is S3, so after last input detected = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   Sequence 101 detected = 1 [OK]

Hint: Follow states step-by-step for each input bit [OK]

Common Mistakes:

• Not updating state on each clock
• Confusing output with input
• Ignoring reset effect

4.

Identify the error in this Verilog code snippet for a sequence detector FSM:

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: if (in == 1) state <= S1;
      S1: if (in == 0) state <= S2;
      S2: if (in == 1) state <= S3;
      S3: state <= S0;
    endcase
  end
end

What is the main problem?

medium

A. Missing default state transition causing latch inference

B. Incorrect sensitivity list in always_ff block

C. Using blocking assignments instead of non-blocking

D. No output signal declared

Solution

1. Step 1: Analyze state transitions

   Each case only assigns state on certain conditions; no else or default to assign state otherwise.

2. Step 2: Understand latch inference

   Missing assignments in some branches cause inferred latches, which is incorrect for FSMs.

3. Final Answer:

   Missing default state transition causing latch inference -> Option A

4. Quick Check:

   All state transitions must be assigned to avoid latches [OK]

Hint: Always assign state in every case branch [OK]

Common Mistakes:

• Not assigning state in else branches
• Using blocking assignments in sequential logic
• Ignoring reset signal

5.

You want to design a sequence detector FSM in Verilog that detects overlapping sequences of "1101" in a serial input stream. Which approach correctly handles overlapping detection?

hard

A. Reset to initial state after full match to allow new detection from next bit

B. Use combinational logic only without states

C. Ignore overlapping sequences and restart detection only after full reset

D. Return to a state representing partial match of last bits to catch overlaps

Solution

1. Step 1: Understand overlapping sequences

   Overlapping means the end of one detected sequence can be the start of another.

2. Step 2: Design FSM to handle overlaps

   FSM must return to a state representing partial match of last bits, not always initial state, to detect overlaps.

3. Final Answer:

   Return to a state representing partial match of last bits to catch overlaps -> Option D

4. Quick Check:

   Partial match states enable overlapping detection [OK]

Hint: Use partial match states to detect overlaps [OK]

Common Mistakes:

• Always resetting to initial state after match
• Ignoring overlap possibility
• Trying to detect sequences without states