Sequence detector FSM in Verilog - Mini Project: Build & Apply

Sequence Detector FSM

📖 Scenario: You are designing a digital circuit that detects a specific sequence of bits on an input signal. This is useful in communication systems where certain patterns trigger actions.

🎯 Goal: Build a finite state machine (FSM) in Verilog that detects the sequence 1011 on a serial input in_bit. The FSM should output 1 on out_seq when the sequence is detected, otherwise 0.

📋 What You'll Learn

Create a Verilog module named seq_detector with inputs clk, reset, and in_bit, and output out_seq.

Define states to track progress through the sequence 1011.

Use a synchronous reset to return to the initial state.

Output out_seq = 1 for one clock cycle when the full sequence is detected.

Use a case statement inside an always block triggered on the rising edge of clk.

💡 Why This Matters

🌍 Real World

Sequence detectors are used in communication protocols to identify control sequences or flags in data streams.

💼 Career

Understanding FSM design in Verilog is essential for hardware engineers working on digital design, FPGA programming, and ASIC development.

1

DATA SETUP: Define module and states

Write a Verilog module named seq_detector with inputs clk, reset, and in_bit, and output out_seq. Inside the module, define a typedef enum logic [2:0] named state_t with states IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, and S1011 = 3'b100. Declare a state variable of type state_t.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
// Define state_t enum and state variable here

// Your code here

endmodule

Need a hint?

Start by declaring the module with the specified inputs and output. Then define the states using typedef enum logic [2:0] and declare a variable state of that type.

2

CONFIGURATION: Initialize state and output

Inside the module, add an always_ff @(posedge clk or posedge reset) block. On reset, set state to IDLE and out_seq to 0. Otherwise, keep out_seq at 0 by default.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
    typedef enum logic [2:0] {IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, S1011 = 3'b100} state_t;
    state_t state;

    always_ff @(posedge clk or posedge reset) begin
        // Initialize state and out_seq on reset
        // Set out_seq to 0 by default
        // Your code here
    end
endmodule

Need a hint?

Use an always_ff block triggered by clk and reset. On reset, assign state to IDLE and out_seq to 0. Otherwise, set out_seq to 0 by default.

3

CORE LOGIC: Implement FSM transitions and output

Inside the else block of the always_ff, add a case statement on state. Implement transitions for detecting the sequence 1011 on in_bit as follows: from IDLE to S1 if in_bit == 1, else stay in IDLE; from S1 to S10 if in_bit == 0, else stay in S1; from S10 to S101 if in_bit == 1, else back to IDLE; from S101 to S1011 if in_bit == 1 else to S1. When in S1011, set out_seq = 1 and transition to S1 if in_bit == 1 else IDLE.

Verilog

            case (state)
                IDLE: if (in_bit) state <= S1; else state <= IDLE;
                S1: if (!in_bit) state <= S10; else state <= S1;
                S10: if (in_bit) state <= S101; else state <= IDLE;
                S101: if (in_bit) state <= S1011; else state <= S1;
                S1011: begin
                    out_seq <= 1;
                    if (in_bit) state <= S1; else state <= IDLE;
                end
                default: state <= IDLE;
            endcase
// Your testbench code here

Need a hint?

Use a case statement on state inside the else block. For each state, check in_bit and update state accordingly. Set out_seq = 1 only in S1011.

4

OUTPUT: Test the FSM with a sample input sequence

Write a testbench module named tb_seq_detector that instantiates seq_detector. Apply a clock with a period of 10 time units. Apply reset for 20 time units at start. Then apply the input bits 1,0,1,1 on in_bit one per clock cycle. Use $display to print the value of out_seq after each clock rising edge.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
    typedef enum logic [2:0] {IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, S1011 = 3'b100} state_t;
    state_t state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_seq <= 0;
        end else begin
            out_seq <= 0;
            case (state)
                IDLE: if (in_bit) state <= S1; else state <= IDLE;
                S1: if (!in_bit) state <= S10; else state <= S1;
                S10: if (in_bit) state <= S101; else state <= IDLE;
                S101: if (in_bit) state <= S1011; else state <= S1;
                S1011: begin
                    out_seq <= 1;
                    if (in_bit) state <= S1; else state <= IDLE;
                end
                default: state <= IDLE;
            endcase
        end
    end
endmodule

module tb_seq_detector();
    logic clk, reset, in_bit;
    logic out_seq;

    seq_detector uut(.clk(clk), .reset(reset), .in_bit(in_bit), .out_seq(out_seq));

    // Your code here
endmodule

Need a hint?

Create a testbench module that generates a clock signal toggling every 5 time units. Apply reset for 20 time units. Then apply the bits 1,0,1,1 on in_bit one per clock cycle. Use $display inside an always_ff @(posedge clk) block to print out_seq.