Sequence detector FSM in Verilog - Mini Project: Build & Apply

Sequence Detector FSM

📖 Scenario: You are designing a digital circuit that detects a specific sequence of bits on an input signal. This is useful in communication systems where certain patterns trigger actions.

🎯 Goal: Build a finite state machine (FSM) in Verilog that detects the sequence 1011 on a serial input in_bit. The FSM should output 1 on out_seq when the sequence is detected, otherwise 0.

📋 What You'll Learn

Create a Verilog module named seq_detector with inputs clk, reset, and in_bit, and output out_seq.

Define states to track progress through the sequence 1011.

Use a synchronous reset to return to the initial state.

Output out_seq = 1 for one clock cycle when the full sequence is detected.

Use a case statement inside an always block triggered on the rising edge of clk.

💡 Why This Matters

🌍 Real World

Sequence detectors are used in communication protocols to identify control sequences or flags in data streams.

💼 Career

Understanding FSM design in Verilog is essential for hardware engineers working on digital design, FPGA programming, and ASIC development.

1

DATA SETUP: Define module and states

Write a Verilog module named seq_detector with inputs clk, reset, and in_bit, and output out_seq. Inside the module, define a typedef enum logic [2:0] named state_t with states IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, and S1011 = 3'b100. Declare a state variable of type state_t.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
// Define state_t enum and state variable here

// Your code here

endmodule

Hint

Start by declaring the module with the specified inputs and output. Then define the states using typedef enum logic [2:0] and declare a variable state of that type.

2

CONFIGURATION: Initialize state and output

Inside the module, add an always_ff @(posedge clk or posedge reset) block. On reset, set state to IDLE and out_seq to 0. Otherwise, keep out_seq at 0 by default.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
    typedef enum logic [2:0] {IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, S1011 = 3'b100} state_t;
    state_t state;

    always_ff @(posedge clk or posedge reset) begin
        // Initialize state and out_seq on reset
        // Set out_seq to 0 by default
        // Your code here
    end
endmodule

Hint

Use an always_ff block triggered by clk and reset. On reset, assign state to IDLE and out_seq to 0. Otherwise, set out_seq to 0 by default.

3

CORE LOGIC: Implement FSM transitions and output

Inside the else block of the always_ff, add a case statement on state. Implement transitions for detecting the sequence 1011 on in_bit as follows: from IDLE to S1 if in_bit == 1, else stay in IDLE; from S1 to S10 if in_bit == 0, else stay in S1; from S10 to S101 if in_bit == 1, else back to IDLE; from S101 to S1011 if in_bit == 1 else to S1. When in S1011, set out_seq = 1 and transition to S1 if in_bit == 1 else IDLE.

Verilog

            case (state)
                IDLE: if (in_bit) state <= S1; else state <= IDLE;
                S1: if (!in_bit) state <= S10; else state <= S1;
                S10: if (in_bit) state <= S101; else state <= IDLE;
                S101: if (in_bit) state <= S1011; else state <= S1;
                S1011: begin
                    out_seq <= 1;
                    if (in_bit) state <= S1; else state <= IDLE;
                end
                default: state <= IDLE;
            endcase
// Your testbench code here

Hint

Use a case statement on state inside the else block. For each state, check in_bit and update state accordingly. Set out_seq = 1 only in S1011.

4

OUTPUT: Test the FSM with a sample input sequence

Write a testbench module named tb_seq_detector that instantiates seq_detector. Apply a clock with a period of 10 time units. Apply reset for 20 time units at start. Then apply the input bits 1,0,1,1 on in_bit one per clock cycle. Use $display to print the value of out_seq after each clock rising edge.

Verilog

module seq_detector(input logic clk, reset, in_bit, output logic out_seq);
    typedef enum logic [2:0] {IDLE = 3'b000, S1 = 3'b001, S10 = 3'b010, S101 = 3'b011, S1011 = 3'b100} state_t;
    state_t state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= IDLE;
            out_seq <= 0;
        end else begin
            out_seq <= 0;
            case (state)
                IDLE: if (in_bit) state <= S1; else state <= IDLE;
                S1: if (!in_bit) state <= S10; else state <= S1;
                S10: if (in_bit) state <= S101; else state <= IDLE;
                S101: if (in_bit) state <= S1011; else state <= S1;
                S1011: begin
                    out_seq <= 1;
                    if (in_bit) state <= S1; else state <= IDLE;
                end
                default: state <= IDLE;
            endcase
        end
    end
endmodule

module tb_seq_detector();
    logic clk, reset, in_bit;
    logic out_seq;

    seq_detector uut(.clk(clk), .reset(reset), .in_bit(in_bit), .out_seq(out_seq));

    // Your code here
endmodule

Hint

Create a testbench module that generates a clock signal toggling every 5 time units. Apply reset for 20 time units. Then apply the bits 1,0,1,1 on in_bit one per clock cycle. Use $display inside an always_ff @(posedge clk) block to print out_seq.

Practice

1.

What is the main purpose of a sequence detector FSM in Verilog?

easy

A. To perform arithmetic operations on input data

B. To detect a specific pattern of bits in a serial input stream

C. To generate random numbers

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM watches input bits and changes states based on the pattern seen.

2. Step 2: Identify purpose

   Its main job is to find a specific bit pattern in a stream and signal when found.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option B

4. Quick Check:

   Sequence detector FSM = pattern detection [OK]

Hint: FSMs track input patterns to signal matches [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does arithmetic

2.

Which of the following is the correct way to declare a state type for a sequence detector FSM in Verilog?

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

easy

A. typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

B. enum state_t {S0, S1, S2, S3};

C. typedef enum {S0, S1, S2, S3} state_t;

D. state_t enum logic [1:0] {S0, S1, S2, S3};

Solution

1. Step 1: Check Verilog enum syntax

   SystemVerilog uses 'typedef enum logic [width] {states} name;' to define state types.

2. Step 2: Match correct syntax

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; matches this syntax exactly, defining 2-bit logic states with typedef.

3. Final Answer:

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; -> Option A

4. Quick Check:

   Correct enum typedef syntax = typedef enum logic [1:0] {S0, S1, S2, S3} state_t; [OK]

Hint: Use 'typedef enum logic [width]' for states in Verilog [OK]

Common Mistakes:

• Omitting 'typedef' keyword
• Missing logic width specification
• Incorrect order of keywords

3.

Given the following Verilog snippet for a sequence detector FSM that detects "101":

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: state <= (in == 1) ? S1 : S0;
      S1: state <= (in == 0) ? S2 : S1;
      S2: state <= (in == 1) ? S3 : S0;
      S3: state <= S0;
    endcase
  end
end

assign detected = (state == S3);

If the input sequence is 1 0 1, what will be the value of detected after the last bit?

medium

A. Undefined

B. 0

C. 1

D. Depends on reset

Solution

1. Step 1: Trace FSM states for input 1,0,1

   Start at S0. Input 1 moves to S1. Input 0 moves to S2. Input 1 moves to S3.

2. Step 2: Check output at S3

   Detected is assigned 1 when state is S3, so after last input detected = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   Sequence 101 detected = 1 [OK]

Hint: Follow states step-by-step for each input bit [OK]

Common Mistakes:

• Not updating state on each clock
• Confusing output with input
• Ignoring reset effect

4.

Identify the error in this Verilog code snippet for a sequence detector FSM:

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: if (in == 1) state <= S1;
      S1: if (in == 0) state <= S2;
      S2: if (in == 1) state <= S3;
      S3: state <= S0;
    endcase
  end
end

What is the main problem?

medium

A. Missing default state transition causing latch inference

B. Incorrect sensitivity list in always_ff block

C. Using blocking assignments instead of non-blocking

D. No output signal declared

Solution

1. Step 1: Analyze state transitions

   Each case only assigns state on certain conditions; no else or default to assign state otherwise.

2. Step 2: Understand latch inference

   Missing assignments in some branches cause inferred latches, which is incorrect for FSMs.

3. Final Answer:

   Missing default state transition causing latch inference -> Option A

4. Quick Check:

   All state transitions must be assigned to avoid latches [OK]

Hint: Always assign state in every case branch [OK]

Common Mistakes:

• Not assigning state in else branches
• Using blocking assignments in sequential logic
• Ignoring reset signal

5.

You want to design a sequence detector FSM in Verilog that detects overlapping sequences of "1101" in a serial input stream. Which approach correctly handles overlapping detection?

hard

A. Reset to initial state after full match to allow new detection from next bit

B. Use combinational logic only without states

C. Ignore overlapping sequences and restart detection only after full reset

D. Return to a state representing partial match of last bits to catch overlaps

Solution

1. Step 1: Understand overlapping sequences

   Overlapping means the end of one detected sequence can be the start of another.

2. Step 2: Design FSM to handle overlaps

   FSM must return to a state representing partial match of last bits, not always initial state, to detect overlaps.

3. Final Answer:

   Return to a state representing partial match of last bits to catch overlaps -> Option D

4. Quick Check:

   Partial match states enable overlapping detection [OK]

Hint: Use partial match states to detect overlaps [OK]

Common Mistakes:

• Always resetting to initial state after match
• Ignoring overlap possibility
• Trying to detect sequences without states