Sequence detector FSM in Verilog - Time & Space Complexity

Time Complexity: Sequence detector FSM

O(n)

Understanding Time Complexity

We want to understand how the time needed to detect a sequence changes as the input grows.

How does the FSM handle longer input streams in terms of steps it takes?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module sequence_detector(
  input clk, reset, in_bit,
  output reg detected
);
  reg [1:0] state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= 0;
    else state <= next_state;
  end

  always @(*) begin
    case(state)
      0: next_state = (in_bit) ? 1 : 0;
      1: next_state = (in_bit) ? 1 : 2;
      2: next_state = (in_bit) ? 3 : 0;
      3: next_state = (in_bit) ? 1 : 2;
      default: next_state = 0;
    endcase
    detected = (state == 3 && in_bit);
  end
endmodule

This code detects the sequence "1101" on a stream of bits using a finite state machine.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The FSM checks one input bit each clock cycle and updates its state.
• How many times: Once per input bit, so it repeats for every bit in the input stream.

How Execution Grows With Input

Each new input bit causes one state update and one check.

Input Size (n)	Approx. Operations
10	10 state updates and checks
100	100 state updates and checks
1000	1000 state updates and checks

Pattern observation: The number of operations grows directly with the number of input bits.

Final Time Complexity

Time Complexity: O(n)

This means the time to detect sequences grows linearly with the input size.

Common Mistake

[X] Wrong: "The FSM checks multiple bits at once, so it runs faster than input size."

[OK] Correct: The FSM processes one bit per clock cycle, so it must check each bit in order, making time grow with input length.

Interview Connect

Understanding how FSMs scale with input size helps you design efficient hardware and explain your reasoning clearly in interviews.

Self-Check

"What if the FSM was designed to detect multiple sequences in parallel? How would the time complexity change?"

Practice

1.

What is the main purpose of a sequence detector FSM in Verilog?

easy

A. To perform arithmetic operations on input data

B. To detect a specific pattern of bits in a serial input stream

C. To generate random numbers

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM watches input bits and changes states based on the pattern seen.

2. Step 2: Identify purpose

   Its main job is to find a specific bit pattern in a stream and signal when found.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option B

4. Quick Check:

   Sequence detector FSM = pattern detection [OK]

Hint: FSMs track input patterns to signal matches [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does arithmetic

2.

Which of the following is the correct way to declare a state type for a sequence detector FSM in Verilog?

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

easy

A. typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

B. enum state_t {S0, S1, S2, S3};

C. typedef enum {S0, S1, S2, S3} state_t;

D. state_t enum logic [1:0] {S0, S1, S2, S3};

Solution

1. Step 1: Check Verilog enum syntax

   SystemVerilog uses 'typedef enum logic [width] {states} name;' to define state types.

2. Step 2: Match correct syntax

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; matches this syntax exactly, defining 2-bit logic states with typedef.

3. Final Answer:

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; -> Option A

4. Quick Check:

   Correct enum typedef syntax = typedef enum logic [1:0] {S0, S1, S2, S3} state_t; [OK]

Hint: Use 'typedef enum logic [width]' for states in Verilog [OK]

Common Mistakes:

• Omitting 'typedef' keyword
• Missing logic width specification
• Incorrect order of keywords

3.

Given the following Verilog snippet for a sequence detector FSM that detects "101":

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: state <= (in == 1) ? S1 : S0;
      S1: state <= (in == 0) ? S2 : S1;
      S2: state <= (in == 1) ? S3 : S0;
      S3: state <= S0;
    endcase
  end
end

assign detected = (state == S3);

If the input sequence is 1 0 1, what will be the value of detected after the last bit?

medium

A. Undefined

B. 0

C. 1

D. Depends on reset

Solution

1. Step 1: Trace FSM states for input 1,0,1

   Start at S0. Input 1 moves to S1. Input 0 moves to S2. Input 1 moves to S3.

2. Step 2: Check output at S3

   Detected is assigned 1 when state is S3, so after last input detected = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   Sequence 101 detected = 1 [OK]

Hint: Follow states step-by-step for each input bit [OK]

Common Mistakes:

• Not updating state on each clock
• Confusing output with input
• Ignoring reset effect

4.

Identify the error in this Verilog code snippet for a sequence detector FSM:

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: if (in == 1) state <= S1;
      S1: if (in == 0) state <= S2;
      S2: if (in == 1) state <= S3;
      S3: state <= S0;
    endcase
  end
end

What is the main problem?

medium

A. Missing default state transition causing latch inference

B. Incorrect sensitivity list in always_ff block

C. Using blocking assignments instead of non-blocking

D. No output signal declared

Solution

1. Step 1: Analyze state transitions

   Each case only assigns state on certain conditions; no else or default to assign state otherwise.

2. Step 2: Understand latch inference

   Missing assignments in some branches cause inferred latches, which is incorrect for FSMs.

3. Final Answer:

   Missing default state transition causing latch inference -> Option A

4. Quick Check:

   All state transitions must be assigned to avoid latches [OK]

Hint: Always assign state in every case branch [OK]

Common Mistakes:

• Not assigning state in else branches
• Using blocking assignments in sequential logic
• Ignoring reset signal

5.

You want to design a sequence detector FSM in Verilog that detects overlapping sequences of "1101" in a serial input stream. Which approach correctly handles overlapping detection?

hard

A. Reset to initial state after full match to allow new detection from next bit

B. Use combinational logic only without states

C. Ignore overlapping sequences and restart detection only after full reset

D. Return to a state representing partial match of last bits to catch overlaps

Solution

1. Step 1: Understand overlapping sequences

   Overlapping means the end of one detected sequence can be the start of another.

2. Step 2: Design FSM to handle overlaps

   FSM must return to a state representing partial match of last bits, not always initial state, to detect overlaps.

3. Final Answer:

   Return to a state representing partial match of last bits to catch overlaps -> Option D

4. Quick Check:

   Partial match states enable overlapping detection [OK]

Hint: Use partial match states to detect overlaps [OK]

Common Mistakes:

• Always resetting to initial state after match
• Ignoring overlap possibility
• Trying to detect sequences without states