ROM (Read-Only Memory) in Verilog - Step-by-Step Execution

Concept Flow - ROM (Read-Only Memory) in Verilog

Start

↓

Address Input

↓

ROM Lookup

↓

Output Data

↓

End

The ROM takes an address input, looks up the stored data at that address, and outputs the data without changing it.

Execution Sample

Verilog

module rom_example(
  input [1:0] addr,
  output reg [3:0] data
);
  always @(*) begin
    case(addr)
      2'b00: data = 4'hA;
      2'b01: data = 4'h3;
      2'b10: data = 4'hF;
      2'b11: data = 4'h0;
      default: data = 4'h0;
    endcase
  end
endmodule

This ROM module outputs a 4-bit value based on a 2-bit address input using a case statement.

Execution Table

Step	Input addr	Condition checked	Data assigned	Output data
1	2'b00	addr == 2'b00	4'hA	1010
2	2'b01	addr == 2'b01	4'h3	0011
3	2'b10	addr == 2'b10	4'hF	1111
4	2'b11	addr == 2'b11	4'h0	0000
5	2'b00	addr == 2'b00	4'hA	1010

💡 ROM outputs data based on address; no state changes or loops, so execution ends after output.

Variable Tracker

Variable	Start	Step 1	Step 2	Step 3	Step 4	Step 5
addr	undefined	2'b00	2'b01	2'b10	2'b11	2'b00
data	undefined	4'hA	4'h3	4'hF	4'h0	4'hA

Key Moments - 2 Insights

Why does the ROM output change immediately when the address changes?

Because the ROM uses a combinational always block (@(*)). It updates output 'data' instantly when 'addr' changes, as shown in execution_table steps 1 to 5.

Is the ROM storing data that can be changed during simulation?

No. The ROM data is fixed in the case statement and does not change during simulation, which is why 'data' only depends on 'addr' input.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output data when addr is 2'b10?

A 4'h3

B 4'h0

C 4'hF

D 4'hA

💡 Hint

Check row 3 in execution_table where addr is 2'b10 and data assigned is 4'hF.

At which step does the ROM output data 4'h0?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at execution_table row 4 where data assigned is 4'h0.

If the address input changes to 2'b01, what will be the output data?

A 4'h3

B 4'hA

C 4'hF

D 4'h0

💡 Hint

Refer to variable_tracker and execution_table rows where addr is 2'b01.

Concept Snapshot

ROM in Verilog stores fixed data accessed by address.
Use combinational always block with case statement.
Input: address; Output: stored data.
Data does not change during simulation.
Outputs update immediately on address change.

Full Transcript

This visual trace shows how a ROM module in Verilog works. The ROM takes a 2-bit address input and outputs a 4-bit data value. The data is fixed and defined in a case statement inside a combinational always block. As the address changes, the output data updates immediately without any delay or state change. The execution table shows each address tested and the corresponding output data. The variable tracker records the address and data values at each step. Key moments clarify why the output changes instantly and why ROM data is read-only. The quiz questions help check understanding of output values for given addresses. This trace helps beginners see how ROM lookup works step-by-step in Verilog.