ROM (Read-Only Memory) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this ROM read operation?

Given the following Verilog ROM module and testbench snippet, what value will be output on data_out when addr = 3'b010?

Verilog

module rom_example(input [2:0] addr, output reg [7:0] data_out);
  reg [7:0] rom [0:7];
  initial begin
    rom[0] = 8'hAA;
    rom[1] = 8'hBB;
    rom[2] = 8'hCC;
    rom[3] = 8'hDD;
    rom[4] = 8'hEE;
    rom[5] = 8'hFF;
    rom[6] = 8'h11;
    rom[7] = 8'h22;
  end
  always @(*) begin
    data_out = rom[addr];
  end
endmodule

// Testbench snippet
// addr = 3'b010;
// Expected data_out = ?

A 8'hDD

B 8'hBB

C 8'hEE

D 8'hCC

💡 Hint

Remember that the address 3'b010 corresponds to decimal 2, so the ROM output is the value stored at index 2.

The ROM is initialized with values at indices 0 to 7. Address 3'b010 is decimal 2, so the output is rom[2], which is 8'hCC.

🧠 Conceptual

intermediate

Which statement about ROM initialization in Verilog is true?

Consider these statements about initializing ROM in Verilog. Which one is correct?

A ROM contents can be initialized using an <code>initial</code> block with explicit assignments.

B ROM contents must be loaded from an external file at runtime only.

C ROM cannot be initialized in Verilog; it must be programmed after synthesis.

D ROM contents are automatically zero unless explicitly written during simulation.

💡 Hint

Think about how Verilog simulation allows setting initial values for memory arrays.

In Verilog, ROM contents can be initialized using an initial block with assignments to the memory array elements. This is common for simulation and synthesis.

🔧 Debug

advanced

Why does this ROM code cause a synthesis error?

Examine this ROM code snippet. Why will it cause a synthesis error?

Verilog

module rom_bug(input clk, input [1:0] addr, output reg [3:0] data_out);
  reg [3:0] rom [0:3];
  always @(posedge clk) begin
    data_out <= rom[addr];
  end
endmodule

A The ROM is not initialized, so synthesis tools cannot infer ROM contents.

B Using <code>always @(posedge clk)</code> with a ROM array causes synthesis error because ROM is combinational.

C The output <code>data_out</code> must be declared as wire, not reg.

D The address width is too small for the ROM size.

💡 Hint

Think about how ROM is usually modeled in Verilog and how synchronous blocks affect synthesis.

ROM is typically modeled as combinational logic in Verilog. Using a clocked always block to read ROM contents can cause synthesis tools to infer unintended registers or cause errors.

📝 Syntax

advanced

Which ROM declaration is syntactically correct in Verilog?

Select the correct way to declare a 16x8-bit ROM in Verilog.

A reg [7:0] rom [0:15];

B reg [15:0] rom [7:0];

C reg rom [7:0][7:0];

D wire [7:0] rom [0:15];

💡 Hint

Remember the syntax for declaring memory arrays in Verilog: reg [width-1:0] name [0:size-1];

Option A correctly declares a memory array with 16 elements, each 8 bits wide. Option A reverses width and size. Option A uses wire which is invalid for memory arrays. Option A uses invalid syntax.

🚀 Application

expert

How many clock cycles does it take to read data from this ROM?

Given this ROM module with synchronous read, how many clock cycles after addr changes will data_out reflect the new data?

Verilog

module rom_sync(input clk, input [3:0] addr, output reg [7:0] data_out);
  reg [7:0] rom [0:15];
  initial begin
    rom[0] = 8'h01; rom[1] = 8'h02; rom[2] = 8'h03; rom[3] = 8'h04;
    // ... initialize other locations
  end
  always @(posedge clk) begin
    data_out <= rom[addr];
  end
endmodule

A Depends on the synthesis tool

B Two clock cycles

C One clock cycle

D Zero clock cycles (immediate combinational output)

💡 Hint

Since the ROM read is inside a clocked block with non-blocking assignment, output updates on the next clock edge.

The ROM read happens on the rising edge of the clock, and the output is registered with a non-blocking assignment. Therefore, data_out updates one clock cycle after addr changes.